Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method /

Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method /

Show other versions (1)

Bibliographic Details
Main Author:	Loy, Ying Ting, 1994-, author 629617
Format:	text
Language:	eng
Published:	Johor Bahru, Johor : Universiti Teknologi Malaysia, 2020

Similar Items

Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method /
by: Loy, Ying Ting, 1994-, author 629617, et al.
Published: (2020)

Optimization of progress parameters for lower leakage current in 10 NM finfet using taguchi method
by: Loy, Ying Ting
Published: (2020)

S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s
by: Jin Hyo Park, et al.
Published: (2021-01-01)

Performance evaluation of 22NM FinFET based 6-T SRAM cell /
by: Fikri Haziq Azmi, 1994-, author
Published: (2017)

Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications
by: Mahmoud S. Badran, et al.
Published: (2019-01-01)

Performance evaluation of 22NM FinFET based 6-T SRAM cell /
by: Fikri Haziq Azmi, 1994-, author, et al.
Published: (2017)

Performance analysis of an efficient montgomery multiplier using 7nm FinFET and junctionless FinFET
by: Mathangi, R., et al.
Published: (2021)

Improvement of the Drive Current in 5nm Bulk-FinFET Using Process and Device Simulations
by: Payman Bahrami, et al.
Published: (2020-02-01)

The Effect of Fin Structure in 5 nm FinFET Technology
by: Enming Shang, et al.
Published: (2019-12-01)

Device simulation of the electrical characteristics in 14nm gaussian channel junctionless finfet /
by: Mathangi Ramakrishnan, 1997-, author 644901
Published: (2022)

Dual Material Pile Gate Approach for Low Leakage Finfet
by: Sanjay S. Chopade, et al.
Published: (2017-01-01)

Performance analysis of 22NM FinFET-based 8T SRAM cell /
by: Nur Hasnifa Hasan Baseri, 1992-, author, et al.
Published: (2018)

Performance analysis of 22NM FinFET-based 8T SRAM cell /
by: Nur Hasnifa Hasan Baseri, 1992-, author, et al.
Published: (2018)

Device simulation of the electrical characteristics in 14nm gaussian channel junctionless finfet /
by: Mathangi Ramakrishnan, 1997-, author 644901, et al.
Published: (2022)

A Device Design for 5 nm Logic FinFET Technology
by: Yu Ding, et al.
Published: (2020-03-01)

Leakage and breakdown mechanisms of GaN vertical power FinFETs
by: Xiao, Ming, et al.
Published: (2019)

Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects
by: Minji Bang, et al.
Published: (2023-05-01)

Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis
by: Mandar S. Bhoir, et al.
Published: (2019-01-01)

Statistical variability in 14NM soi finfet device in the presence of random discrete dopants /
by: Rahimah Hassan, 1992-, author 646943, et al.
Published: (2017)

Process parameter optimization of a 30nm junction-less nanowire transistor for low leakage current /
by: Muhammad Faidzal Mohamad Rasol, author, et al.
Published: (2019)

Process parameter optimization of a 30nm junction-less nanowire transistor for low leakage current /
by: Muhammad Faidzal Mohamad Rasol, author, et al.
Published: (2019)

Performance analysis of 22NM FinFET-based 8T SRAM cell
by: Hasan Baseri, Nur Hasnifa
Published: (2018)

Device simulation of the electrical characteristics in 14nm gaussian channel junctionless finfet
by: Ramakrishnan, Mathangi
Published: (2022)

Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing
by: Amol D. Gaidhane, et al.
Published: (2023-01-01)

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology
by: Marcel Kossel, et al.
Published: (2023-12-01)

Comparison of bulk FinFET and SOI FinFET
by: Chen Ying-Yu, et al.
Published: (2018-01-01)

Self-aligned InGaAs FinFETs with 5-nm fin-width and 5-nm gate-contact separation
by: Vardi, Alon, et al.
Published: (2020)

Sub-60-mV/decade Negative Capacitance FinFET With Sub-10-nm Hafnium-Based Ferroelectric Capacitor
by: Eunah Ko, et al.
Published: (2017-01-01)

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs
by: Shivendra Singh Parihar, et al.
Published: (2023-01-01)

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA
by: Justin Sobas, et al.
Published: (2023-12-01)

Test Structures for the Characterization of the Gate Resistance in 16 nm FinFET RF Transistors
by: Mario Lauritano, et al.
Published: (2023-07-01)

Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs
by: Peng Lu, et al.
Published: (2021-12-01)

Statistical variability in 14NM soi finfet device in the presence of random discrete dopants [electronic resource] /
by: Rahimah Hassan, 1992-, author 646943, et al.
Published: (2017)

A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs
by: Shivendra Singh Parihar, et al.
Published: (2023-01-01)

Detectors Array for In Situ Electron Beam Imaging by 16-nm FinFET CMOS Technology
by: Chien-Ping Wang, et al.
Published: (2021-05-01)

Fault injection and failure analysis on Xilinx 16 nm FinFET Ultrascale+ MPSoC
by: Weitao Yang, et al.
Published: (2022-06-01)

Optimization of 20nm junctionless nanowire transistor using Taguchi method for higher drive current with strained /
by: Nurul Liyana Nasuha Omar, 1996-, author, et al.
Published: (2019)

Optimization of 20nm junctionless nanowire transistor using Taguchi method for higher drive current with strained /
by: Nurul Liyana Nasuha Omar, 1996-, author, et al.
Published: (2019)

10-nm Fin-width InGaSb p-channel self-aligned FinFETs using antimonide-compatible digital etch
by: Lu, Wenjie, et al.
Published: (2020)

Performance evaluation of finfet silicide based contact through electrical simulation /
by: Muhammad Adli Aini 1994- author 633499
Published: (2021)