MATHEMATICAL MODELLING AND OPTIMIZATION OF MULTISITE EFFICIENCY TO REDUCE COST OF TEST IN SEMICONDUCTOR FINAL TEST PROCESS USING TAGUCHI METHOD /
| Main Authors: | , , , , |
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| Format: | text |
| Language: | eng |
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Johor Bahru, Johor : Universiti Teknologi Malaysia,
2021
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| _version_ | 1811129032620638208 |
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| author | Khoo Voon Ching, 1974-, author 654412 Rozzeta Dolah, supervisor 186505 Habibah Haron, supervisor 610493 Puvanesvaran Gunalan, supervisor 654413 Fakulti Teknologi dan Informatik Razak 619091 |
| author_facet | Khoo Voon Ching, 1974-, author 654412 Rozzeta Dolah, supervisor 186505 Habibah Haron, supervisor 610493 Puvanesvaran Gunalan, supervisor 654413 Fakulti Teknologi dan Informatik Razak 619091 |
| author_sort | Khoo Voon Ching, 1974-, author 654412 |
| collection | OCEAN |
| description | |
| first_indexed | 2024-03-05T17:31:46Z |
| format | text |
| id | KOHA-OAI-TEST:610422 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-09-23T23:41:43Z |
| publishDate | 2021 |
| publisher | Johor Bahru, Johor : Universiti Teknologi Malaysia, |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:6104222024-09-02T02:34:29ZMATHEMATICAL MODELLING AND OPTIMIZATION OF MULTISITE EFFICIENCY TO REDUCE COST OF TEST IN SEMICONDUCTOR FINAL TEST PROCESS USING TAGUCHI METHOD / Khoo Voon Ching, 1974-, author 654412 Rozzeta Dolah, supervisor 186505 Habibah Haron, supervisor 610493 Puvanesvaran Gunalan, supervisor 654413 Fakulti Teknologi dan Informatik Razak 619091 textJohor Bahru, Johor : Universiti Teknologi Malaysia, 2021engIncludes bibliographyKK-FTIRSemiconductorsTaguchi methods (Quality control) |
| spellingShingle | Semiconductors Taguchi methods (Quality control) Khoo Voon Ching, 1974-, author 654412 Rozzeta Dolah, supervisor 186505 Habibah Haron, supervisor 610493 Puvanesvaran Gunalan, supervisor 654413 Fakulti Teknologi dan Informatik Razak 619091 MATHEMATICAL MODELLING AND OPTIMIZATION OF MULTISITE EFFICIENCY TO REDUCE COST OF TEST IN SEMICONDUCTOR FINAL TEST PROCESS USING TAGUCHI METHOD / |
| title | MATHEMATICAL MODELLING AND OPTIMIZATION OF MULTISITE EFFICIENCY TO REDUCE COST OF TEST IN SEMICONDUCTOR FINAL TEST PROCESS USING TAGUCHI METHOD / |
| title_full | MATHEMATICAL MODELLING AND OPTIMIZATION OF MULTISITE EFFICIENCY TO REDUCE COST OF TEST IN SEMICONDUCTOR FINAL TEST PROCESS USING TAGUCHI METHOD / |
| title_fullStr | MATHEMATICAL MODELLING AND OPTIMIZATION OF MULTISITE EFFICIENCY TO REDUCE COST OF TEST IN SEMICONDUCTOR FINAL TEST PROCESS USING TAGUCHI METHOD / |
| title_full_unstemmed | MATHEMATICAL MODELLING AND OPTIMIZATION OF MULTISITE EFFICIENCY TO REDUCE COST OF TEST IN SEMICONDUCTOR FINAL TEST PROCESS USING TAGUCHI METHOD / |
| title_short | MATHEMATICAL MODELLING AND OPTIMIZATION OF MULTISITE EFFICIENCY TO REDUCE COST OF TEST IN SEMICONDUCTOR FINAL TEST PROCESS USING TAGUCHI METHOD / |
| title_sort | mathematical modelling and optimization of multisite efficiency to reduce cost of test in semiconductor final test process using taguchi method |
| topic | Semiconductors Taguchi methods (Quality control) |
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