Verilog design of input / output processor with built-in-self-test /
Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik)) - Fakulti Kejuruteraan Elektrik, Universiti Teknologi Malaysia, 2007
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| Format: | |
| Language: | eng |
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Skudai : Universiti Teknologi Malaysia,
2007
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| Online Access: | http://www.psz.utm.my/sla/billing/login.asp?mid=49217 |
| _version_ | 1796661286883295232 |
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| author | 425851 Goh, Keng Hoo |
| author_facet | 425851 Goh, Keng Hoo |
| author_sort | 425851 Goh, Keng Hoo |
| collection | OCEAN |
| description | Thesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik)) - Fakulti Kejuruteraan Elektrik, Universiti Teknologi Malaysia, 2007 |
| first_indexed | 2024-03-04T16:30:40Z |
| format | |
| id | KOHA-OAI-TEST:80632 |
| institution | Universiti Teknologi Malaysia - OCEAN |
| language | eng |
| last_indexed | 2024-03-04T16:30:40Z |
| publishDate | 2007 |
| publisher | Skudai : Universiti Teknologi Malaysia, |
| record_format | dspace |
| spelling | KOHA-OAI-TEST:806322020-12-19T17:00:33ZVerilog design of input / output processor with built-in-self-test / 425851 Goh, Keng Hoo Skudai : Universiti Teknologi Malaysia,2007engThesis (Sarjana Kejuruteraan (Elektrik - Komputer dan Mikroelektronik)) - Fakulti Kejuruteraan Elektrik, Universiti Teknologi Malaysia, 200716FEELECTLVerilog (Computer hardware description language)http://www.psz.utm.my/sla/billing/login.asp?mid=49217 |
| spellingShingle | Verilog (Computer hardware description language) 425851 Goh, Keng Hoo Verilog design of input / output processor with built-in-self-test / |
| title | Verilog design of input / output processor with built-in-self-test / |
| title_full | Verilog design of input / output processor with built-in-self-test / |
| title_fullStr | Verilog design of input / output processor with built-in-self-test / |
| title_full_unstemmed | Verilog design of input / output processor with built-in-self-test / |
| title_short | Verilog design of input / output processor with built-in-self-test / |
| title_sort | verilog design of input output processor with built in self test |
| topic | Verilog (Computer hardware description language) |
| url | http://www.psz.utm.my/sla/billing/login.asp?mid=49217 |
| work_keys_str_mv | AT 425851gohkenghoo verilogdesignofinputoutputprocessorwithbuiltinselftest |