Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell

This paper represents the impact of nanowires ratio of silicon nanowire transistors on the characteristics of 6-transistors SRAM cell. This study is the first to demonstrate nanowires ratio optimization of Nano-scale SiNWT Based SRAM Cell. Noise margins and inflection voltage of transfer character...

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Main Authors: Naif, Yasir Hasyim, Alsibai, Mohammad Hayyan, Abdul Manap, Sulastri
Format: Article
Language:English
Published: EDP Sciences, 2015 2015
Subjects:
Online Access:http://umpir.ump.edu.my/id/eprint/11600/1/matecconf_iceim2015_01009.pdf
_version_ 1825822669529939968
author Naif, Yasir Hasyim
Alsibai, Mohammad Hayyan
Abdul Manap, Sulastri
author_facet Naif, Yasir Hasyim
Alsibai, Mohammad Hayyan
Abdul Manap, Sulastri
author_sort Naif, Yasir Hasyim
collection UMP
description This paper represents the impact of nanowires ratio of silicon nanowire transistors on the characteristics of 6-transistors SRAM cell. This study is the first to demonstrate nanowires ratio optimization of Nano-scale SiNWT Based SRAM Cell. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both nanowires ratio and digital voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decreasing in optimization ratio but with increasing in current and power. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower dimensions and lower inflection currents and then with lower power consumption.
first_indexed 2024-03-06T12:00:03Z
format Article
id UMPir11600
institution Universiti Malaysia Pahang
language English
last_indexed 2024-03-06T12:00:03Z
publishDate 2015
publisher EDP Sciences, 2015
record_format dspace
spelling UMPir116002018-02-02T07:15:02Z http://umpir.ump.edu.my/id/eprint/11600/ Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell Naif, Yasir Hasyim Alsibai, Mohammad Hayyan Abdul Manap, Sulastri Not Available This paper represents the impact of nanowires ratio of silicon nanowire transistors on the characteristics of 6-transistors SRAM cell. This study is the first to demonstrate nanowires ratio optimization of Nano-scale SiNWT Based SRAM Cell. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both nanowires ratio and digital voltage level (Vdd). And increasing of logic voltage level from 1V to 3V tends to decreasing in optimization ratio but with increasing in current and power. SRAM using nanowires transistors must use logic level (2V or 2.5V) to produce SRAM with lower dimensions and lower inflection currents and then with lower power consumption. EDP Sciences, 2015 2015 Article PeerReviewed application/pdf en cc_by http://umpir.ump.edu.my/id/eprint/11600/1/matecconf_iceim2015_01009.pdf Naif, Yasir Hasyim and Alsibai, Mohammad Hayyan and Abdul Manap, Sulastri (2015) Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell. MATEC Web of Conferences, 27. pp. 1-5. ISSN 2261-236X. (Published) http://dx.doi.org/10.1051/matecconf/20152701009 10.1051/matecconf/20152701009
spellingShingle Not Available
Naif, Yasir Hasyim
Alsibai, Mohammad Hayyan
Abdul Manap, Sulastri
Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell
title Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell
title_full Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell
title_fullStr Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell
title_full_unstemmed Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell
title_short Optimization of Nanowires Ratio in Nano-scale SiNWT Based SRAM Cell
title_sort optimization of nanowires ratio in nano scale sinwt based sram cell
topic Not Available
url http://umpir.ump.edu.my/id/eprint/11600/1/matecconf_iceim2015_01009.pdf
work_keys_str_mv AT naifyasirhasyim optimizationofnanowiresratioinnanoscalesinwtbasedsramcell
AT alsibaimohammadhayyan optimizationofnanowiresratioinnanoscalesinwtbasedsramcell
AT abdulmanapsulastri optimizationofnanowiresratioinnanoscalesinwtbasedsramcell