Nanowire NMOS Logic Inverter Characterization
This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce stat...
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| Format: | Article |
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American Scientific Publishers
2016
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| _version_ | 1825822898485460992 |
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| author | Naif, Yasir Hashim |
| author_facet | Naif, Yasir Hashim |
| author_sort | Naif, Yasir Hashim |
| collection | UMP |
| description | This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly. |
| first_indexed | 2024-03-06T12:03:23Z |
| format | Article |
| id | UMPir12987 |
| institution | Universiti Malaysia Pahang |
| last_indexed | 2024-03-06T12:03:23Z |
| publishDate | 2016 |
| publisher | American Scientific Publishers |
| record_format | dspace |
| spelling | UMPir129872017-08-22T06:52:12Z http://umpir.ump.edu.my/id/eprint/12987/ Nanowire NMOS Logic Inverter Characterization Naif, Yasir Hashim TK Electrical engineering. Electronics Nuclear engineering This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly. American Scientific Publishers 2016-06 Article PeerReviewed Naif, Yasir Hashim (2016) Nanowire NMOS Logic Inverter Characterization. Journal of Nanoscience and Nanotechnology, 16 (6). pp. 5923-5928. ISSN 1533-4880 (Print); 1533-4899 (Online). (Published) http://www.aspbs.com/jnn/ |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Naif, Yasir Hashim Nanowire NMOS Logic Inverter Characterization |
| title | Nanowire NMOS Logic Inverter Characterization |
| title_full | Nanowire NMOS Logic Inverter Characterization |
| title_fullStr | Nanowire NMOS Logic Inverter Characterization |
| title_full_unstemmed | Nanowire NMOS Logic Inverter Characterization |
| title_short | Nanowire NMOS Logic Inverter Characterization |
| title_sort | nanowire nmos logic inverter characterization |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| work_keys_str_mv | AT naifyasirhashim nanowirenmoslogicinvertercharacterization |