Design and implementation of advanced encryption standard using verilog HDL
Encryption plays an important role in data security against third-party attacks and it is significant to safeguard sensitive data and personal information for the community. Within this era of technology, privacy and confidentiality are the essential considerations to be addressed as a result of the...
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| Format: | Conference or Workshop Item |
| Language: | English English |
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Springer Science and Business Media Deutschland GmbH
2022
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| Online Access: | http://umpir.ump.edu.my/id/eprint/37557/1/Design%20and%20implementation%20of%20advanced%20encryption%20standard%20using%20verilog%20HDL.pdf http://umpir.ump.edu.my/id/eprint/37557/2/Design%20and%20implementation%20of%20advanced%20encryption%20standard%20using_ABS.pdf |
| _version_ | 1825814953393651712 |
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| author | Shamsiah, Suhaili Fredrick, Rene Brooke Zainah, Md. Zain Norhuzaimin, Julai |
| author_facet | Shamsiah, Suhaili Fredrick, Rene Brooke Zainah, Md. Zain Norhuzaimin, Julai |
| author_sort | Shamsiah, Suhaili |
| collection | UMP |
| description | Encryption plays an important role in data security against third-party attacks and it is significant to safeguard sensitive data and personal information for the community. Within this era of technology, privacy and confidentiality are the essential considerations to be addressed as a result of the exponential development of the Internet. One of the main concerns involving software implementation of encryption algorithm is the possibility of slower processing when transmitting and receiving data which consequently will encounter low security level during process of encryption for real-time application. The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. Real-time application is essential for today’s modern world and Field Programmable Gate Array approach is applied for this purpose. The optimization approaches include loop release, pipeline architecture and Look-Up-Table (LUT) which allow for exact synchronization in order to meet applications’ requirements in real time. The design is coded using the Verilog HDL and the hardware design is analyzed and tested with Altera Cyclone II-V in Quartus II and ModelSim. Through comparative analysis with previous implementation, the maximum throughput for this design is 31.37 Gbit/s for the encryption process can operate at 244.89 MHz. The complete 128-bit AES encryption cycle requires only 41 clock cycles to get the encrypted data. |
| first_indexed | 2024-03-06T13:06:13Z |
| format | Conference or Workshop Item |
| id | UMPir37557 |
| institution | Universiti Malaysia Pahang |
| language | English English |
| last_indexed | 2024-03-06T13:06:13Z |
| publishDate | 2022 |
| publisher | Springer Science and Business Media Deutschland GmbH |
| record_format | dspace |
| spelling | UMPir375572023-08-28T01:28:28Z http://umpir.ump.edu.my/id/eprint/37557/ Design and implementation of advanced encryption standard using verilog HDL Shamsiah, Suhaili Fredrick, Rene Brooke Zainah, Md. Zain Norhuzaimin, Julai T Technology (General) TA Engineering (General). Civil engineering (General) TK Electrical engineering. Electronics Nuclear engineering Encryption plays an important role in data security against third-party attacks and it is significant to safeguard sensitive data and personal information for the community. Within this era of technology, privacy and confidentiality are the essential considerations to be addressed as a result of the exponential development of the Internet. One of the main concerns involving software implementation of encryption algorithm is the possibility of slower processing when transmitting and receiving data which consequently will encounter low security level during process of encryption for real-time application. The focus of this paper is to match with the existing cryptography algorithm, 128-bit Advanced Encryption Algorithm and improving the processing speed for the design with hardware implementation. Real-time application is essential for today’s modern world and Field Programmable Gate Array approach is applied for this purpose. The optimization approaches include loop release, pipeline architecture and Look-Up-Table (LUT) which allow for exact synchronization in order to meet applications’ requirements in real time. The design is coded using the Verilog HDL and the hardware design is analyzed and tested with Altera Cyclone II-V in Quartus II and ModelSim. Through comparative analysis with previous implementation, the maximum throughput for this design is 31.37 Gbit/s for the encryption process can operate at 244.89 MHz. The complete 128-bit AES encryption cycle requires only 41 clock cycles to get the encrypted data. Springer Science and Business Media Deutschland GmbH 2022 Conference or Workshop Item PeerReviewed pdf en http://umpir.ump.edu.my/id/eprint/37557/1/Design%20and%20implementation%20of%20advanced%20encryption%20standard%20using%20verilog%20HDL.pdf pdf en http://umpir.ump.edu.my/id/eprint/37557/2/Design%20and%20implementation%20of%20advanced%20encryption%20standard%20using_ABS.pdf Shamsiah, Suhaili and Fredrick, Rene Brooke and Zainah, Md. Zain and Norhuzaimin, Julai (2022) Design and implementation of advanced encryption standard using verilog HDL. In: Lecture Notes in Electrical Engineering; 12th National Technical Seminar on Unmanned System Technology, NUSYS 2020 , 24-25 November 2020 , Virtual, Online. pp. 483-498., 770. ISSN 1876-1100 ISBN 978-981162405-6 (Published) https://doi.org/10.1007/978-981-16-2406-3_37 |
| spellingShingle | T Technology (General) TA Engineering (General). Civil engineering (General) TK Electrical engineering. Electronics Nuclear engineering Shamsiah, Suhaili Fredrick, Rene Brooke Zainah, Md. Zain Norhuzaimin, Julai Design and implementation of advanced encryption standard using verilog HDL |
| title | Design and implementation of advanced encryption standard using verilog HDL |
| title_full | Design and implementation of advanced encryption standard using verilog HDL |
| title_fullStr | Design and implementation of advanced encryption standard using verilog HDL |
| title_full_unstemmed | Design and implementation of advanced encryption standard using verilog HDL |
| title_short | Design and implementation of advanced encryption standard using verilog HDL |
| title_sort | design and implementation of advanced encryption standard using verilog hdl |
| topic | T Technology (General) TA Engineering (General). Civil engineering (General) TK Electrical engineering. Electronics Nuclear engineering |
| url | http://umpir.ump.edu.my/id/eprint/37557/1/Design%20and%20implementation%20of%20advanced%20encryption%20standard%20using%20verilog%20HDL.pdf http://umpir.ump.edu.my/id/eprint/37557/2/Design%20and%20implementation%20of%20advanced%20encryption%20standard%20using_ABS.pdf |
| work_keys_str_mv | AT shamsiahsuhaili designandimplementationofadvancedencryptionstandardusingveriloghdl AT fredrickrenebrooke designandimplementationofadvancedencryptionstandardusingveriloghdl AT zainahmdzain designandimplementationofadvancedencryptionstandardusingveriloghdl AT norhuzaiminjulai designandimplementationofadvancedencryptionstandardusingveriloghdl |