Chess digital clock
The purpose of my project is to design and implement of the Chess Digital Clock. The project employs ISE software (ISE Design Suite 10.1) and implementation on Field-Programmable Gate Arrays (FPGAs) Xilinx board. It is a new technique for testing the interconnects of an arbitrary design mapped into...
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| Format: | Undergraduates Project Papers |
| Language: | English |
| Published: |
2008
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| Online Access: | http://umpir.ump.edu.my/id/eprint/499/1/02.Chess%20digital%20clock.pdf |