An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
Combinatorial logic circuit minimization is usualy done using Karnaugh’s Map or Bolean equation. This paper presents an aplication of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmar...
| Main Authors: | , , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
2014
|
| Subjects: | |
| Online Access: | http://umpir.ump.edu.my/id/eprint/7831/1/An_Experimental_Study_Of_Combinational_Logic_Circuit_Minimization_Using_Firefly_Algorithm.pdf |
| _version_ | 1796990339628662784 |
|---|---|
| author | Aznilnda, Zainodin Aida Khairunisa, Ab. Kadir M. Nasir, Ayob Ahmad Fariz, Hasan Amar Faiz, Zainal Abidin Fazlinashatul Suhaidah, Zahid Hazriq Izuan, Jafar Ismail, Mohd Khairuddin |
| author_facet | Aznilnda, Zainodin Aida Khairunisa, Ab. Kadir M. Nasir, Ayob Ahmad Fariz, Hasan Amar Faiz, Zainal Abidin Fazlinashatul Suhaidah, Zahid Hazriq Izuan, Jafar Ismail, Mohd Khairuddin |
| author_sort | Aznilnda, Zainodin |
| collection | UMP |
| description | Combinatorial logic circuit minimization is usualy done using Karnaugh’s Map or Bolean equation. This paper presents an aplication of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial ogic circuit minimization |
| first_indexed | 2024-03-06T11:50:08Z |
| format | Article |
| id | UMPir7831 |
| institution | Universiti Malaysia Pahang |
| language | English |
| last_indexed | 2024-03-06T11:50:08Z |
| publishDate | 2014 |
| record_format | dspace |
| spelling | UMPir78312018-02-28T03:58:01Z http://umpir.ump.edu.my/id/eprint/7831/ An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm Aznilnda, Zainodin Aida Khairunisa, Ab. Kadir M. Nasir, Ayob Ahmad Fariz, Hasan Amar Faiz, Zainal Abidin Fazlinashatul Suhaidah, Zahid Hazriq Izuan, Jafar Ismail, Mohd Khairuddin TS Manufactures Combinatorial logic circuit minimization is usualy done using Karnaugh’s Map or Bolean equation. This paper presents an aplication of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial ogic circuit minimization 2014 Article PeerReviewed application/pdf en http://umpir.ump.edu.my/id/eprint/7831/1/An_Experimental_Study_Of_Combinational_Logic_Circuit_Minimization_Using_Firefly_Algorithm.pdf Aznilnda, Zainodin and Aida Khairunisa, Ab. Kadir and M. Nasir, Ayob and Ahmad Fariz, Hasan and Amar Faiz, Zainal Abidin and Fazlinashatul Suhaidah, Zahid and Hazriq Izuan, Jafar and Ismail, Mohd Khairuddin (2014) An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm. Coloquium on Robotics, Unmaned Systems And Cybernetics 2014 (CRUSC 2014). pp. 17-21. (Published) |
| spellingShingle | TS Manufactures Aznilnda, Zainodin Aida Khairunisa, Ab. Kadir M. Nasir, Ayob Ahmad Fariz, Hasan Amar Faiz, Zainal Abidin Fazlinashatul Suhaidah, Zahid Hazriq Izuan, Jafar Ismail, Mohd Khairuddin An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm |
| title | An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm |
| title_full | An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm |
| title_fullStr | An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm |
| title_full_unstemmed | An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm |
| title_short | An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm |
| title_sort | experimental study of combinational logic circuit minimization using firefly algorithm |
| topic | TS Manufactures |
| url | http://umpir.ump.edu.my/id/eprint/7831/1/An_Experimental_Study_Of_Combinational_Logic_Circuit_Minimization_Using_Firefly_Algorithm.pdf |
| work_keys_str_mv | AT aznilndazainodin anexperimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT aidakhairunisaabkadir anexperimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT mnasirayob anexperimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT ahmadfarizhasan anexperimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT amarfaizzainalabidin anexperimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT fazlinashatulsuhaidahzahid anexperimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT hazriqizuanjafar anexperimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT ismailmohdkhairuddin anexperimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT aznilndazainodin experimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT aidakhairunisaabkadir experimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT mnasirayob experimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT ahmadfarizhasan experimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT amarfaizzainalabidin experimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT fazlinashatulsuhaidahzahid experimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT hazriqizuanjafar experimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm AT ismailmohdkhairuddin experimentalstudyofcombinationallogiccircuitminimizationusingfireflyalgorithm |