Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the se...

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Bibliographic Details
Main Authors: Gijin Park, Jaeduk Han, Woorham Bae
Format: Article
Language:English
Published: MDPI AG 2021-10-01
Series:Electronics
Subjects:
clock generation
duty cycle
asynchronous sampling
calibration
analysis
Online Access:https://www.mdpi.com/2079-9292/10/21/2594

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