An adjustable 0.3 V current winner‐take‐all circuit for analogue neural networks
Abstract This letter presents an upgraded winner‐take‐all (WTA) circuit that is capable of operating under low‐voltage supplies. The proposed circuit re‐configures the basic loop of a conventional WTA through an auxiliary transistor to decrease the dropped voltage across the tail current. This recon...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-08-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ell2.12156 |
| Summary: | Abstract This letter presents an upgraded winner‐take‐all (WTA) circuit that is capable of operating under low‐voltage supplies. The proposed circuit re‐configures the basic loop of a conventional WTA through an auxiliary transistor to decrease the dropped voltage across the tail current. This reconfiguration creates an additional biasing voltage providing more adjustability. Moreover, the new feedback path decreases the delay compared to the conventional WTA. Both conventional and proposed WTAs were fabricated in the TSMC 0.18 μm CMOS technology. The experimental results show a 29.4 and 33.2 μs reduction in rising and falling times, respectively, for the proposed WTA under a supply voltage of 0.3 V. |
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| ISSN: | 0013-5194 1350-911X |