A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse
This article presents a fully integrated bidirectional class-G digital Doherty switched capacitor transmitter (TX) and N-path Quadrature receiver (RX) in CMOS. Through sharing on-chip capacitor banks, typically occupying a major portion of the digital TX or RX chip area, as well as the RF passive ma...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9936623/ |
| _version_ | 1811233373212901376 |
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| author | Jeongseok Lee Doohwan Jung David Munzer Hua Wang |
| author_facet | Jeongseok Lee Doohwan Jung David Munzer Hua Wang |
| author_sort | Jeongseok Lee |
| collection | DOAJ |
| description | This article presents a fully integrated bidirectional class-G digital Doherty switched capacitor transmitter (TX) and N-path Quadrature receiver (RX) in CMOS. Through sharing on-chip capacitor banks, typically occupying a major portion of the digital TX or RX chip area, as well as the RF passive matching networks, the overall size can be radically reduced. Moreover, the overall performance could be further improved by eliminating the need for an integrated T/RX switch and its corresponding loss and area overhead. The class-G operation is used within the Doherty TX to increase the output power and backoff efficiency, while the capacitive stacking technique is used in the RX to increase the voltage gain. A transformer network is used to present the optimum impedance for both the parallel Doherty TX and RX mode of operation, as well as the class-G Doherty active load modulation. As a proof-of-concept, the joint bidirectional class-G digital Doherty switched-capacitor TX and N-path Quadrature RX through capacitor bank sharing is implemented in a 45-nm CMOS SOI process. The TX demonstrates a <inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm {out}}~1$ </tex-math></inline-formula>dB bandwidth (BW) of 1.6-3.1 GHz, a fractional BW >63%, and peak output power (<inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm {out}}$ </tex-math></inline-formula>) of 22.5dBm at 2.4GHz. The peak drain efficiency (DE) of the TX is 49.5% at 1.8GHz and 41.5%/38.7%/31.6%/18.1% for the peak/2.5/6/12dB power back off (PBO) at 2.4GHz. The DE improvement compared to class-B PA is <inline-formula> <tex-math notation="LaTeX">$1.24\times /1.51\times /1.72\times $ </tex-math></inline-formula> at 2.5/6/12dB PBO. The TX is measured using 64-QAM/20MHz modulation without the use of AM-PM pre-distortion or pattern based DPD. It achieves an excellent −27.1dB EVM, −31.31dBc ACLR, 14.6dBm average <inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm {out}}$ </tex-math></inline-formula> and 25.8% average DE at 1.6GHz. The RX achieves a noise figure (NF) of 7.6dB at 2.2GHz and a conversion gain of 17dB with a 12 MHz bandwidth. In addition, the proposed RX front-end achieves <inline-formula> <tex-math notation="LaTeX">$ < -60$ </tex-math></inline-formula> dBm LO leakage over the operating frequency range |
| first_indexed | 2024-04-12T11:19:36Z |
| format | Article |
| id | doaj.art-02ca3e846fac4631bb6b1960c91f2b36 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-12T11:19:36Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
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| series | IEEE Access |
| spelling | doaj.art-02ca3e846fac4631bb6b1960c91f2b362022-12-22T03:35:25ZengIEEEIEEE Access2169-35362022-01-011011709311710410.1109/ACCESS.2022.32190569936623A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network ReuseJeongseok Lee0https://orcid.org/0000-0002-2803-1314Doohwan Jung1https://orcid.org/0000-0002-3852-8164David Munzer2https://orcid.org/0000-0002-4059-3731Hua Wang3School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USASchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USASchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USASchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USAThis article presents a fully integrated bidirectional class-G digital Doherty switched capacitor transmitter (TX) and N-path Quadrature receiver (RX) in CMOS. Through sharing on-chip capacitor banks, typically occupying a major portion of the digital TX or RX chip area, as well as the RF passive matching networks, the overall size can be radically reduced. Moreover, the overall performance could be further improved by eliminating the need for an integrated T/RX switch and its corresponding loss and area overhead. The class-G operation is used within the Doherty TX to increase the output power and backoff efficiency, while the capacitive stacking technique is used in the RX to increase the voltage gain. A transformer network is used to present the optimum impedance for both the parallel Doherty TX and RX mode of operation, as well as the class-G Doherty active load modulation. As a proof-of-concept, the joint bidirectional class-G digital Doherty switched-capacitor TX and N-path Quadrature RX through capacitor bank sharing is implemented in a 45-nm CMOS SOI process. The TX demonstrates a <inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm {out}}~1$ </tex-math></inline-formula>dB bandwidth (BW) of 1.6-3.1 GHz, a fractional BW >63%, and peak output power (<inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm {out}}$ </tex-math></inline-formula>) of 22.5dBm at 2.4GHz. The peak drain efficiency (DE) of the TX is 49.5% at 1.8GHz and 41.5%/38.7%/31.6%/18.1% for the peak/2.5/6/12dB power back off (PBO) at 2.4GHz. The DE improvement compared to class-B PA is <inline-formula> <tex-math notation="LaTeX">$1.24\times /1.51\times /1.72\times $ </tex-math></inline-formula> at 2.5/6/12dB PBO. The TX is measured using 64-QAM/20MHz modulation without the use of AM-PM pre-distortion or pattern based DPD. It achieves an excellent −27.1dB EVM, −31.31dBc ACLR, 14.6dBm average <inline-formula> <tex-math notation="LaTeX">$\text{P}_{\mathrm {out}}$ </tex-math></inline-formula> and 25.8% average DE at 1.6GHz. The RX achieves a noise figure (NF) of 7.6dB at 2.2GHz and a conversion gain of 17dB with a 12 MHz bandwidth. In addition, the proposed RX front-end achieves <inline-formula> <tex-math notation="LaTeX">$ < -60$ </tex-math></inline-formula> dBm LO leakage over the operating frequency rangehttps://ieeexplore.ieee.org/document/9936623/Capacitor stackingclass-G DPACMOSdigital front-enddohertylinearity |
| spellingShingle | Jeongseok Lee Doohwan Jung David Munzer Hua Wang A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse IEEE Access Capacitor stacking class-G DPA CMOS digital front-end doherty linearity |
| title | A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse |
| title_full | A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse |
| title_fullStr | A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse |
| title_full_unstemmed | A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse |
| title_short | A Compact CMOS Broadband Bidirectional Digital Transceiver Frontend With Capacitor Bank and Transformer Matching Network Reuse |
| title_sort | compact cmos broadband bidirectional digital transceiver frontend with capacitor bank and transformer matching network reuse |
| topic | Capacitor stacking class-G DPA CMOS digital front-end doherty linearity |
| url | https://ieeexplore.ieee.org/document/9936623/ |
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