| Summary: | Recent reports of silent data corruption because of hardware faults in large data centers bring to the forefront the importance of in-field testing. In-field testing, enabled by logic built-in self-test (<inline-formula> <tex-math notation="LaTeX">$LBIST$ </tex-math></inline-formula>), addresses defects that occur during the lifetime of a chip and ones that escaped manufacturing tests. A class of <inline-formula> <tex-math notation="LaTeX">$LBIST$ </tex-math></inline-formula> approaches for scan circuits store partitioned deterministic test data on-chip and produce tests by combining stored test data entries in one of two ways: 1) pseudo-random combinations are selected by linear-feedback shift-registers (<inline-formula> <tex-math notation="LaTeX">$LFSR\text{s}$ </tex-math></inline-formula>); or 2) deterministic combinations are stored on-chip as sets of indices of stored test data entries. This article introduces a third option where counters are used for forming combinations of stored test data entries. Counters do not require additional storage, and ensure complete fault coverage with a limited number of tests. Experimental results for benchmark circuits demonstrate the advantages of counters in the context where test data entries for on-chip storage are obtained by partitioning compressed deterministic tests, and the universally available on-chip decompression logic is used as part of the test application process.
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