Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing
To improve the test accuracy and fault coverage of high-speed railway-related equipment boards, a time-varying pseudorandom disturbance algorithm based on the automatic test pattern generation technology in chip testing is proposed. The algorithm combines the pseudorandom pattern generation algorith...
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Format: | Article |
Language: | English |
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MDPI AG
2022-05-01
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Series: | Micromachines |
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Online Access: | https://www.mdpi.com/2072-666X/13/6/853 |
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author | Xiaoming Chen Zhixuan Wang Zhiyang Yu Hsiang-Chen Chui |
author_facet | Xiaoming Chen Zhixuan Wang Zhiyang Yu Hsiang-Chen Chui |
author_sort | Xiaoming Chen |
collection | DOAJ |
description | To improve the test accuracy and fault coverage of high-speed railway-related equipment boards, a time-varying pseudorandom disturbance algorithm based on the automatic test pattern generation technology in chip testing is proposed. The algorithm combines the pseudorandom pattern generation algorithm with the deterministic pattern generation D algorithm. The existing pseudorandom number generation method usually requires random seeds to generate a series of pseudorandom numbers. In this algorithm, the system timer is used as the random seed to design a pseudorandom pattern generation method of time-varying seed to improve the randomness of pseudorandom pattern generation. In addition, in combination with the D algorithm, this work proposes a new switching logic between two algorithms by counting invalid pattern proportions. When the algorithm is applied to track a circuit netlist, the fault coverage can reach near 100%. However, the large-scale circuit fault coverage cannot easily reach 100%. The test results for the standard circuits of different sizes show that at the same time, compared with the independent pattern generation methods, the proposed algorithm can improve fault coverage by more than 50% and 30% and significantly improve the pattern generation efficiency. Therefore, it can be used perfectly in the subsequent construction of high-speed railway equipment test platforms. |
first_indexed | 2024-03-09T23:01:37Z |
format | Article |
id | doaj.art-03f0e7a21876484b81e210254deda5ee |
institution | Directory Open Access Journal |
issn | 2072-666X |
language | English |
last_indexed | 2024-03-09T23:01:37Z |
publishDate | 2022-05-01 |
publisher | MDPI AG |
record_format | Article |
series | Micromachines |
spelling | doaj.art-03f0e7a21876484b81e210254deda5ee2023-11-23T18:00:26ZengMDPI AGMicromachines2072-666X2022-05-0113685310.3390/mi13060853Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment TestingXiaoming Chen0Zhixuan Wang1Zhiyang Yu2Hsiang-Chen Chui3School of Optoelectronic Engineering and Instrumentation Science, Dalian University of Technology, Dalian 116000, ChinaSchool of Optoelectronic Engineering and Instrumentation Science, Dalian University of Technology, Dalian 116000, ChinaSignal and Communication Research Institute, China Academy of Railway Sciences Corporation Limited, Beijing 100081, ChinaSchool of Optoelectronic Engineering and Instrumentation Science, Dalian University of Technology, Dalian 116000, ChinaTo improve the test accuracy and fault coverage of high-speed railway-related equipment boards, a time-varying pseudorandom disturbance algorithm based on the automatic test pattern generation technology in chip testing is proposed. The algorithm combines the pseudorandom pattern generation algorithm with the deterministic pattern generation D algorithm. The existing pseudorandom number generation method usually requires random seeds to generate a series of pseudorandom numbers. In this algorithm, the system timer is used as the random seed to design a pseudorandom pattern generation method of time-varying seed to improve the randomness of pseudorandom pattern generation. In addition, in combination with the D algorithm, this work proposes a new switching logic between two algorithms by counting invalid pattern proportions. When the algorithm is applied to track a circuit netlist, the fault coverage can reach near 100%. However, the large-scale circuit fault coverage cannot easily reach 100%. The test results for the standard circuits of different sizes show that at the same time, compared with the independent pattern generation methods, the proposed algorithm can improve fault coverage by more than 50% and 30% and significantly improve the pattern generation efficiency. Therefore, it can be used perfectly in the subsequent construction of high-speed railway equipment test platforms.https://www.mdpi.com/2072-666X/13/6/853high-speed railwayATPG 2pseudorandom pattern 3D algorithm 4 |
spellingShingle | Xiaoming Chen Zhixuan Wang Zhiyang Yu Hsiang-Chen Chui Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing Micromachines high-speed railway ATPG 2 pseudorandom pattern 3 D algorithm 4 |
title | Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing |
title_full | Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing |
title_fullStr | Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing |
title_full_unstemmed | Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing |
title_short | Time-Varying Pseudorandom Disturbed Pattern Generation Algorithm for Track Circuit Equipment Testing |
title_sort | time varying pseudorandom disturbed pattern generation algorithm for track circuit equipment testing |
topic | high-speed railway ATPG 2 pseudorandom pattern 3 D algorithm 4 |
url | https://www.mdpi.com/2072-666X/13/6/853 |
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