Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations
Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2011-04-01
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| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | http://www.mdpi.com/2079-9268/1/1/97/ |
| _version_ | 1798026890735255552 |
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| author | Marco Lanuzza Fabio Frustaci Stefania Perri Pasquale Corsonello |
| author_facet | Marco Lanuzza Fabio Frustaci Stefania Perri Pasquale Corsonello |
| author_sort | Marco Lanuzza |
| collection | DOAJ |
| description | Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS) standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures) operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal. |
| first_indexed | 2024-04-11T18:42:33Z |
| format | Article |
| id | doaj.art-04a254a33336439bb27a9296579bdb44 |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-11T18:42:33Z |
| publishDate | 2011-04-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-04a254a33336439bb27a9296579bdb442022-12-22T04:08:56ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682011-04-01119710810.3390/jlpea1010097Design of Energy Aware Adder Circuits Considering Random Intra-Die Process VariationsMarco LanuzzaFabio FrustaciStefania PerriPasquale CorsonelloEnergy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS) standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures) operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal.http://www.mdpi.com/2079-9268/1/1/97/intra-die process variationsyield-driven designadder design |
| spellingShingle | Marco Lanuzza Fabio Frustaci Stefania Perri Pasquale Corsonello Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations Journal of Low Power Electronics and Applications intra-die process variations yield-driven design adder design |
| title | Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations |
| title_full | Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations |
| title_fullStr | Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations |
| title_full_unstemmed | Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations |
| title_short | Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations |
| title_sort | design of energy aware adder circuits considering random intra die process variations |
| topic | intra-die process variations yield-driven design adder design |
| url | http://www.mdpi.com/2079-9268/1/1/97/ |
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