Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer
Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS's search complexity is smaller than the s...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Stefan cel Mare University of Suceava
2013-02-01
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| Series: | Advances in Electrical and Computer Engineering |
| Subjects: | |
| Online Access: | http://dx.doi.org/10.4316/AECE.2013.01002 |
| _version_ | 1818511523527524352 |
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| author | HOO, C.-S. JEEVAN, K. GANAPATHY, V. RAMIAH, H. |
| author_facet | HOO, C.-S. JEEVAN, K. GANAPATHY, V. RAMIAH, H. |
| author_sort | HOO, C.-S. |
| collection | DOAJ |
| description | Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS. |
| first_indexed | 2024-12-10T23:34:19Z |
| format | Article |
| id | doaj.art-04d4dcd41e394560b94416164ebc322f |
| institution | Directory Open Access Journal |
| issn | 1582-7445 1844-7600 |
| language | English |
| last_indexed | 2024-12-10T23:34:19Z |
| publishDate | 2013-02-01 |
| publisher | Stefan cel Mare University of Suceava |
| record_format | Article |
| series | Advances in Electrical and Computer Engineering |
| spelling | doaj.art-04d4dcd41e394560b94416164ebc322f2022-12-22T01:29:14ZengStefan cel Mare University of SuceavaAdvances in Electrical and Computer Engineering1582-74451844-76002013-02-01131131610.4316/AECE.2013.01002Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module PlacerHOO, C.-S.JEEVAN, K.GANAPATHY, V.RAMIAH, H.Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS) is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS), CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC) hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.http://dx.doi.org/10.4316/AECE.2013.01002designsystemaidedfloorplanningVLSIrepresentationcircuitsalgorithmscaleoptimization |
| spellingShingle | HOO, C.-S. JEEVAN, K. GANAPATHY, V. RAMIAH, H. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer Advances in Electrical and Computer Engineering design system aided floorplanning VLSI representation circuits algorithm scale optimization |
| title | Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer |
| title_full | Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer |
| title_fullStr | Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer |
| title_full_unstemmed | Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer |
| title_short | Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer |
| title_sort | ant system corner insertion sequence an efficient vlsi hard module placer |
| topic | design system aided floorplanning VLSI representation circuits algorithm scale optimization |
| url | http://dx.doi.org/10.4316/AECE.2013.01002 |
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