Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs
As the performance of digital devices is improving, Hardware-In-the-Loop (HIL) techniques are being increasingly used. HIL systems are frequently implemented using FPGAs (Field Programmable Gate Array) as they allow faster calculations and therefore smaller simulation steps. As the simulation step i...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2018-09-01
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| Series: | Electronics |
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| Online Access: | http://www.mdpi.com/2079-9292/7/10/219 |
| _version_ | 1798041900474695680 |
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| author | Alberto Sanchez Elías Todorovich Angel de Castro |
| author_facet | Alberto Sanchez Elías Todorovich Angel de Castro |
| author_sort | Alberto Sanchez |
| collection | DOAJ |
| description | As the performance of digital devices is improving, Hardware-In-the-Loop (HIL) techniques are being increasingly used. HIL systems are frequently implemented using FPGAs (Field Programmable Gate Array) as they allow faster calculations and therefore smaller simulation steps. As the simulation step is reduced, the incremental values for the state variables are reduced proportionally, increasing the difference between the current value of the state variable and its increments. This difference can lead to numerical resolution issues when both magnitudes cannot be stored simultaneously in the state variable. FPGA-based HIL systems generally use 32-bit floating-point due to hardware and timing restrictions but they may suffer from these resolution problems. This paper explores the limits of 32-bit floating-point arithmetics in the context of hardware-in-the-loop systems, and how a larger format can be used to avoid resolution problems. The consequences in terms of hardware resources and running frequency are also explored. Although the conclusions reached in this work can be applied to any digital device, they can be directly used in the field of FPGAs, where the designer can easily use custom floating-point arithmetics. |
| first_indexed | 2024-04-11T22:28:02Z |
| format | Article |
| id | doaj.art-0535c1bea748465e88bab950c352d498 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-04-11T22:28:02Z |
| publishDate | 2018-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-0535c1bea748465e88bab950c352d4982022-12-22T03:59:36ZengMDPI AGElectronics2079-92922018-09-0171021910.3390/electronics7100219electronics7100219Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAsAlberto Sanchez0Elías Todorovich1Angel de Castro2HCTLab Research Group, Universidad Autonoma de Madrid, 28049 Madrid, SpainFacultad de Ciencias Exactas, Universidad Nacional del Centro de la Provincia de Buenos Aires, Tandil B7001BBO, ArgentinaHCTLab Research Group, Universidad Autonoma de Madrid, 28049 Madrid, SpainAs the performance of digital devices is improving, Hardware-In-the-Loop (HIL) techniques are being increasingly used. HIL systems are frequently implemented using FPGAs (Field Programmable Gate Array) as they allow faster calculations and therefore smaller simulation steps. As the simulation step is reduced, the incremental values for the state variables are reduced proportionally, increasing the difference between the current value of the state variable and its increments. This difference can lead to numerical resolution issues when both magnitudes cannot be stored simultaneously in the state variable. FPGA-based HIL systems generally use 32-bit floating-point due to hardware and timing restrictions but they may suffer from these resolution problems. This paper explores the limits of 32-bit floating-point arithmetics in the context of hardware-in-the-loop systems, and how a larger format can be used to avoid resolution problems. The consequences in terms of hardware resources and running frequency are also explored. Although the conclusions reached in this work can be applied to any digital device, they can be directly used in the field of FPGAs, where the designer can easily use custom floating-point arithmetics.http://www.mdpi.com/2079-9292/7/10/219hardware-in-the-loopfloating-pointfixed-pointreal-time emulationfield programmable gate array |
| spellingShingle | Alberto Sanchez Elías Todorovich Angel de Castro Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs Electronics hardware-in-the-loop floating-point fixed-point real-time emulation field programmable gate array |
| title | Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs |
| title_full | Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs |
| title_fullStr | Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs |
| title_full_unstemmed | Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs |
| title_short | Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs |
| title_sort | exploring the limits of floating point resolution for hardware in the loop implemented with fpgas |
| topic | hardware-in-the-loop floating-point fixed-point real-time emulation field programmable gate array |
| url | http://www.mdpi.com/2079-9292/7/10/219 |
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