A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor
This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locki...
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9045937/ |
| _version_ | 1818577911516495872 |
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| author | Muhammad Riaz Ur Rehman Arash Hejazi Imran Ali Jae Jin Lee Seong Jin Oh Younggun Pu Kang-Yoon Lee |
| author_facet | Muhammad Riaz Ur Rehman Arash Hejazi Imran Ali Jae Jin Lee Seong Jin Oh Younggun Pu Kang-Yoon Lee |
| author_sort | Muhammad Riaz Ur Rehman |
| collection | DOAJ |
| description | This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). In the lock state, the ACC value dithers due to the closed loop operation. A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. It helps the jitter reduction in the ADDLL. Additionally, it provides robustness against glitches, false locking and unlocking in a noisy environment. The ADDLL peak to peak jitter and RMS jitter at 625 MHz are 6.5 ps and 1.2 ps respectively. The ADDLL including DCDC is implemented on $0.18~\mu \text{m}$ CMOS technology with an operational range of 350~900 MHz. It consumes only 6.8 mW at 625 MHz power with 1.8 V power supply. The area utilization is 0.06 mm<sup>2</sup>. |
| first_indexed | 2024-12-16T06:37:26Z |
| format | Article |
| id | doaj.art-0615578ba8544ce18e198d85b7edbdae |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-16T06:37:26Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-0615578ba8544ce18e198d85b7edbdae2022-12-21T22:40:46ZengIEEEIEEE Access2169-35362020-01-018577225773210.1109/ACCESS.2020.29821809045937A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging SensorMuhammad Riaz Ur Rehman0Arash Hejazi1Imran Ali2Jae Jin Lee3Seong Jin Oh4Younggun Pu5Kang-Yoon Lee6https://orcid.org/0000-0001-9777-6953College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaCollege of Information and Communication Engineering, Sungkyunkwan University, Suwon, South KoreaThis paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). In the lock state, the ACC value dithers due to the closed loop operation. A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. It helps the jitter reduction in the ADDLL. Additionally, it provides robustness against glitches, false locking and unlocking in a noisy environment. The ADDLL peak to peak jitter and RMS jitter at 625 MHz are 6.5 ps and 1.2 ps respectively. The ADDLL including DCDC is implemented on $0.18~\mu \text{m}$ CMOS technology with an operational range of 350~900 MHz. It consumes only 6.8 mW at 625 MHz power with 1.8 V power supply. The area utilization is 0.06 mm<sup>2</sup>.https://ieeexplore.ieee.org/document/9045937/All digital delay locked loop (ADDLL)digital controllerjitterlight detection and ranging (LIDAR)time to digital converter (TDC) |
| spellingShingle | Muhammad Riaz Ur Rehman Arash Hejazi Imran Ali Jae Jin Lee Seong Jin Oh Younggun Pu Kang-Yoon Lee A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor IEEE Access All digital delay locked loop (ADDLL) digital controller jitter light detection and ranging (LIDAR) time to digital converter (TDC) |
| title | A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor |
| title_full | A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor |
| title_fullStr | A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor |
| title_full_unstemmed | A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor |
| title_short | A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor |
| title_sort | design of 6 8 mw all digital delay locked loop with digitally controlled dither cancellation for tdc in ranging sensor |
| topic | All digital delay locked loop (ADDLL) digital controller jitter light detection and ranging (LIDAR) time to digital converter (TDC) |
| url | https://ieeexplore.ieee.org/document/9045937/ |
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