Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing
Memory is the biggest limiting factor to the widespread use of FPGAs for high-level image processing, which require complete frame(s) to be stored in situ. Since FPGAs have limited on-chip memory capabilities, efficient use of such resources is essential to meet performance, size and power constrain...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2019-01-01
|
| Series: | Journal of Imaging |
| Subjects: | |
| Online Access: | http://www.mdpi.com/2313-433X/5/1/7 |
| _version_ | 1818032054696148992 |
|---|---|
| author | Paulo Garcia Deepayan Bhowmik Robert Stewart Greg Michaelson Andrew Wallace |
| author_facet | Paulo Garcia Deepayan Bhowmik Robert Stewart Greg Michaelson Andrew Wallace |
| author_sort | Paulo Garcia |
| collection | DOAJ |
| description | Memory is the biggest limiting factor to the widespread use of FPGAs for high-level image processing, which require complete frame(s) to be stored in situ. Since FPGAs have limited on-chip memory capabilities, efficient use of such resources is essential to meet performance, size and power constraints. In this paper, we investigate allocation of on-chip memory resources in order to minimize resource usage and power consumption, contributing to the realization of power-efficient high-level image processing fully contained on FPGAs. We propose methods for generating memory architectures, from both Hardware Description Languages and High Level Synthesis designs, which minimize memory usage and power consumption. Based on a formalization of on-chip memory configuration options and a power model, we demonstrate how our partitioning algorithms can outperform traditional strategies. Compared to commercial FPGA synthesis and High Level Synthesis tools, our results show that the proposed algorithms can result in up to 60% higher utilization efficiency, increasing the sizes and/or number of frames that can be accommodated, and reduce frame buffers’ dynamic power consumption by up to approximately 70%. In our experiments using Optical Flow and MeanShift Tracking, representative high-level algorithms, data show that partitioning algorithms can reduce total power by up to 25% and 30%, respectively, without impacting performance. |
| first_indexed | 2024-12-10T06:01:16Z |
| format | Article |
| id | doaj.art-063afaf3065d44ada4c2368f54a74639 |
| institution | Directory Open Access Journal |
| issn | 2313-433X |
| language | English |
| last_indexed | 2024-12-10T06:01:16Z |
| publishDate | 2019-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Imaging |
| spelling | doaj.art-063afaf3065d44ada4c2368f54a746392022-12-22T01:59:48ZengMDPI AGJournal of Imaging2313-433X2019-01-0151710.3390/jimaging5010007jimaging5010007Optimized Memory Allocation and Power Minimization for FPGA-Based Image ProcessingPaulo Garcia0Deepayan Bhowmik1Robert Stewart2Greg Michaelson3Andrew Wallace4Department of Systems and Computer Engineering, Carleton University, Ottawa, ON K1S 5B6, CanadaDiv. of Computing Science and Mathematics, University of Stirling, Stirling FK9 4LA, UKSchool of Mathematical and Computer Sciences, Heriot Watt University, Edinburgh EH14 4AS, UKSchool of Mathematical and Computer Sciences, Heriot Watt University, Edinburgh EH14 4AS, UKSchool of Engineering and Physical Sciences, Heriot Watt University, Edinburgh EH14 4AS, UKMemory is the biggest limiting factor to the widespread use of FPGAs for high-level image processing, which require complete frame(s) to be stored in situ. Since FPGAs have limited on-chip memory capabilities, efficient use of such resources is essential to meet performance, size and power constraints. In this paper, we investigate allocation of on-chip memory resources in order to minimize resource usage and power consumption, contributing to the realization of power-efficient high-level image processing fully contained on FPGAs. We propose methods for generating memory architectures, from both Hardware Description Languages and High Level Synthesis designs, which minimize memory usage and power consumption. Based on a formalization of on-chip memory configuration options and a power model, we demonstrate how our partitioning algorithms can outperform traditional strategies. Compared to commercial FPGA synthesis and High Level Synthesis tools, our results show that the proposed algorithms can result in up to 60% higher utilization efficiency, increasing the sizes and/or number of frames that can be accommodated, and reduce frame buffers’ dynamic power consumption by up to approximately 70%. In our experiments using Optical Flow and MeanShift Tracking, representative high-level algorithms, data show that partitioning algorithms can reduce total power by up to 25% and 30%, respectively, without impacting performance.http://www.mdpi.com/2313-433X/5/1/7field programmable gate array (FPGA)memorypowerimage processingdesign |
| spellingShingle | Paulo Garcia Deepayan Bhowmik Robert Stewart Greg Michaelson Andrew Wallace Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing Journal of Imaging field programmable gate array (FPGA) memory power image processing design |
| title | Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing |
| title_full | Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing |
| title_fullStr | Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing |
| title_full_unstemmed | Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing |
| title_short | Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing |
| title_sort | optimized memory allocation and power minimization for fpga based image processing |
| topic | field programmable gate array (FPGA) memory power image processing design |
| url | http://www.mdpi.com/2313-433X/5/1/7 |
| work_keys_str_mv | AT paulogarcia optimizedmemoryallocationandpowerminimizationforfpgabasedimageprocessing AT deepayanbhowmik optimizedmemoryallocationandpowerminimizationforfpgabasedimageprocessing AT robertstewart optimizedmemoryallocationandpowerminimizationforfpgabasedimageprocessing AT gregmichaelson optimizedmemoryallocationandpowerminimizationforfpgabasedimageprocessing AT andrewwallace optimizedmemoryallocationandpowerminimizationforfpgabasedimageprocessing |