A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC
This article presents an accurate quadrature phase-locked loop (PLL) with quadrature phase mismatch calibration for 32 GS/s analog-to-digital converter (ADC). Due to the mismatches of clock distribution in layout and variations of the active devices, the quadrature phase of the sampling clock is sig...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9286446/ |