Specially-Designed Out-of-Order Processor Architecture for Microcontrollers
In very large-scale integration circuit (VLSI) systems, microcontrollers are often implanted to manage the whole system to complete the given computing tasks. They play an essential part as regulators, which should allocate resources steadily and issue instructions promptly to drive functional units...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-09-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/19/2989 |
| _version_ | 1797479900924346368 |
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| author | Yunhao Hu Jie Chen Kaiben Zhu Qijun Xing Wei Liu Junfeng Shen Ge Gao |
| author_facet | Yunhao Hu Jie Chen Kaiben Zhu Qijun Xing Wei Liu Junfeng Shen Ge Gao |
| author_sort | Yunhao Hu |
| collection | DOAJ |
| description | In very large-scale integration circuit (VLSI) systems, microcontrollers are often implanted to manage the whole system to complete the given computing tasks. They play an essential part as regulators, which should allocate resources steadily and issue instructions promptly to drive functional units. However, most of the recent research focuses on the operation at the software level or the scheduling at the SoC level, ignoring the impact of the microarchitecture and the features of controlled sub-modules. This paper analyzes the requirements of microcontrollers in the VLSI system with various constraints and conditions that should be considered in the hardware implementation of such microarchitecture. Furthermore, this paper takes an open-source design using RISC-V ISA as the prototype to implement hardware microarchitecture. This design integrates the techniques of out-of-order processing, which are usually used on superscalar processors. As a result, the design quadruples the number of pipelined instructions, greatly alleviating the stalling of the instruction stream with a maximum extra look up table utilization of 18.37% in FPGA implementation. |
| first_indexed | 2024-03-09T21:52:26Z |
| format | Article |
| id | doaj.art-07799f9b9d5544bdbaa92fd328e97430 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T21:52:26Z |
| publishDate | 2022-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-07799f9b9d5544bdbaa92fd328e974302023-11-23T20:04:26ZengMDPI AGElectronics2079-92922022-09-011119298910.3390/electronics11192989Specially-Designed Out-of-Order Processor Architecture for MicrocontrollersYunhao Hu0Jie Chen1Kaiben Zhu2Qijun Xing3Wei Liu4Junfeng Shen5Ge Gao6School of Physics and Technology, Wuhan University, Wuhan 430072, ChinaSchool of Physics and Technology, Wuhan University, Wuhan 430072, ChinaSchool of Physics and Technology, Wuhan University, Wuhan 430072, ChinaSchool of Physics and Technology, Wuhan University, Wuhan 430072, ChinaSchool of Physics and Technology, Wuhan University, Wuhan 430072, ChinaCollege of Biology and Agricultural Resources, Huanggang Normal University, Huanggang 438000, ChinaSchool of Computer Science, Wuhan University, Wuhan 430072, ChinaIn very large-scale integration circuit (VLSI) systems, microcontrollers are often implanted to manage the whole system to complete the given computing tasks. They play an essential part as regulators, which should allocate resources steadily and issue instructions promptly to drive functional units. However, most of the recent research focuses on the operation at the software level or the scheduling at the SoC level, ignoring the impact of the microarchitecture and the features of controlled sub-modules. This paper analyzes the requirements of microcontrollers in the VLSI system with various constraints and conditions that should be considered in the hardware implementation of such microarchitecture. Furthermore, this paper takes an open-source design using RISC-V ISA as the prototype to implement hardware microarchitecture. This design integrates the techniques of out-of-order processing, which are usually used on superscalar processors. As a result, the design quadruples the number of pipelined instructions, greatly alleviating the stalling of the instruction stream with a maximum extra look up table utilization of 18.37% in FPGA implementation.https://www.mdpi.com/2079-9292/11/19/2989microcontrollerout-of-ordermicroarchitectureRISC-Vhardware implementation |
| spellingShingle | Yunhao Hu Jie Chen Kaiben Zhu Qijun Xing Wei Liu Junfeng Shen Ge Gao Specially-Designed Out-of-Order Processor Architecture for Microcontrollers Electronics microcontroller out-of-order microarchitecture RISC-V hardware implementation |
| title | Specially-Designed Out-of-Order Processor Architecture for Microcontrollers |
| title_full | Specially-Designed Out-of-Order Processor Architecture for Microcontrollers |
| title_fullStr | Specially-Designed Out-of-Order Processor Architecture for Microcontrollers |
| title_full_unstemmed | Specially-Designed Out-of-Order Processor Architecture for Microcontrollers |
| title_short | Specially-Designed Out-of-Order Processor Architecture for Microcontrollers |
| title_sort | specially designed out of order processor architecture for microcontrollers |
| topic | microcontroller out-of-order microarchitecture RISC-V hardware implementation |
| url | https://www.mdpi.com/2079-9292/11/19/2989 |
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