Tolerating Permanent Faults in the Input Port of the Network on Chip Router
Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large num...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2019-02-01
|
| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9268/9/1/11 |
| _version_ | 1798041308511600640 |
|---|---|
| author | Hala J. Mohammed Wameedh N. Flayyih Fakhrul Z. Rokhani |
| author_facet | Hala J. Mohammed Wameedh N. Flayyih Fakhrul Z. Rokhani |
| author_sort | Hala J. Mohammed |
| collection | DOAJ |
| description | Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure. |
| first_indexed | 2024-04-11T22:19:45Z |
| format | Article |
| id | doaj.art-081487baecfd4acb88ca60d2852e519c |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-11T22:19:45Z |
| publishDate | 2019-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-081487baecfd4acb88ca60d2852e519c2022-12-22T04:00:14ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682019-02-01911110.3390/jlpea9010011jlpea9010011Tolerating Permanent Faults in the Input Port of the Network on Chip RouterHala J. Mohammed0Wameedh N. Flayyih1Fakhrul Z. Rokhani2Department of Computer Engineering, College of Engineering, University of Baghdad, Baghdad 10071, IraqDepartment of Computer Engineering, College of Engineering, University of Baghdad, Baghdad 10071, IraqSystem-on-Chip Research Center & MyAgeing Research Institute, Universiti Putra Malaysia, Serdang 43400, MalaysiaDeep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.https://www.mdpi.com/2079-9268/9/1/11NoCreliabilitypermanent faultsfault tolerance |
| spellingShingle | Hala J. Mohammed Wameedh N. Flayyih Fakhrul Z. Rokhani Tolerating Permanent Faults in the Input Port of the Network on Chip Router Journal of Low Power Electronics and Applications NoC reliability permanent faults fault tolerance |
| title | Tolerating Permanent Faults in the Input Port of the Network on Chip Router |
| title_full | Tolerating Permanent Faults in the Input Port of the Network on Chip Router |
| title_fullStr | Tolerating Permanent Faults in the Input Port of the Network on Chip Router |
| title_full_unstemmed | Tolerating Permanent Faults in the Input Port of the Network on Chip Router |
| title_short | Tolerating Permanent Faults in the Input Port of the Network on Chip Router |
| title_sort | tolerating permanent faults in the input port of the network on chip router |
| topic | NoC reliability permanent faults fault tolerance |
| url | https://www.mdpi.com/2079-9268/9/1/11 |
| work_keys_str_mv | AT halajmohammed toleratingpermanentfaultsintheinputportofthenetworkonchiprouter AT wameedhnflayyih toleratingpermanentfaultsintheinputportofthenetworkonchiprouter AT fakhrulzrokhani toleratingpermanentfaultsintheinputportofthenetworkonchiprouter |