A Heterogeneous Inference Framework for a Deep Neural Network
Artificial intelligence (AI) is one of the most promising technologies based on machine learning algorithms. In this paper, we propose a workflow for the implementation of deep neural networks. This workflow attempts to combine the flexibility of high-level compilers (HLS)-based networks with the ar...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2024-01-01
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| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/13/2/348 |
| _version_ | 1797344192887783424 |
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| author | Rafael Gadea-Gironés José Luís Rocabado-Rocha Jorge Fe Jose M. Monzo |
| author_facet | Rafael Gadea-Gironés José Luís Rocabado-Rocha Jorge Fe Jose M. Monzo |
| author_sort | Rafael Gadea-Gironés |
| collection | DOAJ |
| description | Artificial intelligence (AI) is one of the most promising technologies based on machine learning algorithms. In this paper, we propose a workflow for the implementation of deep neural networks. This workflow attempts to combine the flexibility of high-level compilers (HLS)-based networks with the architectural control features of hardware description languages (HDL)-based flows. The architecture consists of a convolutional neural network, SqueezeNet v1.1, and a hard processor system (HPS) that coexists with acceleration hardware to be designed. This methodology allows us to compare solutions based solely on software (PyTorch 1.13.1) and propose heterogeneous inference solutions, taking advantage of the best options within the software and hardware flow. The proposed workflow is implemented on a low-cost field programmable gate array system-on-chip (FPGA SOC) platform, specifically the DE10-Nano development board. We have provided systolic architectural solutions written in OpenCL that are highly flexible and easily tunable to take full advantage of the resources of programmable devices and achieve superior energy efficiencies working with a 32-bit floating point. From a verification point of view, the proposed method is effective, since the reference models in all tests, both for the individual layers and the complete network, have been readily available using packages well known in the development, training, and inference of deep networks. |
| first_indexed | 2024-03-08T10:58:48Z |
| format | Article |
| id | doaj.art-0870dde17e514bdeb0cfe7b0a5c3ffd4 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-08T10:58:48Z |
| publishDate | 2024-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-0870dde17e514bdeb0cfe7b0a5c3ffd42024-01-26T16:14:01ZengMDPI AGElectronics2079-92922024-01-0113234810.3390/electronics13020348A Heterogeneous Inference Framework for a Deep Neural NetworkRafael Gadea-Gironés0José Luís Rocabado-Rocha1Jorge Fe2Jose M. Monzo3Institute for Molecular Imaging Technologies (I3M), Universitat Politècnica de València, 46022 Valencia, SpainInstitute for Molecular Imaging Technologies (I3M), Universitat Politècnica de València, 46022 Valencia, SpainInstitute for Molecular Imaging Technologies (I3M), Universitat Politècnica de València, 46022 Valencia, SpainInstitute for Molecular Imaging Technologies (I3M), Universitat Politècnica de València, 46022 Valencia, SpainArtificial intelligence (AI) is one of the most promising technologies based on machine learning algorithms. In this paper, we propose a workflow for the implementation of deep neural networks. This workflow attempts to combine the flexibility of high-level compilers (HLS)-based networks with the architectural control features of hardware description languages (HDL)-based flows. The architecture consists of a convolutional neural network, SqueezeNet v1.1, and a hard processor system (HPS) that coexists with acceleration hardware to be designed. This methodology allows us to compare solutions based solely on software (PyTorch 1.13.1) and propose heterogeneous inference solutions, taking advantage of the best options within the software and hardware flow. The proposed workflow is implemented on a low-cost field programmable gate array system-on-chip (FPGA SOC) platform, specifically the DE10-Nano development board. We have provided systolic architectural solutions written in OpenCL that are highly flexible and easily tunable to take full advantage of the resources of programmable devices and achieve superior energy efficiencies working with a 32-bit floating point. From a verification point of view, the proposed method is effective, since the reference models in all tests, both for the individual layers and the complete network, have been readily available using packages well known in the development, training, and inference of deep networks.https://www.mdpi.com/2079-9292/13/2/348convolutional neural networksheterogeneous computationsystolic arraysFPGA |
| spellingShingle | Rafael Gadea-Gironés José Luís Rocabado-Rocha Jorge Fe Jose M. Monzo A Heterogeneous Inference Framework for a Deep Neural Network Electronics convolutional neural networks heterogeneous computation systolic arrays FPGA |
| title | A Heterogeneous Inference Framework for a Deep Neural Network |
| title_full | A Heterogeneous Inference Framework for a Deep Neural Network |
| title_fullStr | A Heterogeneous Inference Framework for a Deep Neural Network |
| title_full_unstemmed | A Heterogeneous Inference Framework for a Deep Neural Network |
| title_short | A Heterogeneous Inference Framework for a Deep Neural Network |
| title_sort | heterogeneous inference framework for a deep neural network |
| topic | convolutional neural networks heterogeneous computation systolic arrays FPGA |
| url | https://www.mdpi.com/2079-9292/13/2/348 |
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