Tabular synthesis of three-variable functions using one-bit full adders(基于一位全加器三变量逻辑函数的查表综合)
通过对1个一位全加器3个输入端不同的组合,可以实现与门、或门、非门、同或门及异或门,因此全加器在数字逻辑电路中有着重要的作用.本文在介绍全加器的基础上提出了用查表法设计基于一位全加器实现任意三变量函数的组合电路和时序电路.在与传统的与非门/或非门的比较中,它显示了优势....
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| Format: | Article |
| Language: | zho |
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Zhejiang University Press
2003-09-01
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| Series: | Zhejiang Daxue xuebao. Lixue ban |
| Subjects: | |
| Online Access: | https://doi.org/zjup/1008-9497.2003.30.5.518-523 |
| _version_ | 1797236324097327104 |
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| author | ZHOUChang(周畅) WUYin-er(伍银儿) CHENXie-xiong(陈偕雄) |
| author_facet | ZHOUChang(周畅) WUYin-er(伍银儿) CHENXie-xiong(陈偕雄) |
| author_sort | ZHOUChang(周畅) |
| collection | DOAJ |
| description | 通过对1个一位全加器3个输入端不同的组合,可以实现与门、或门、非门、同或门及异或门,因此全加器在数字逻辑电路中有着重要的作用.本文在介绍全加器的基础上提出了用查表法设计基于一位全加器实现任意三变量函数的组合电路和时序电路.在与传统的与非门/或非门的比较中,它显示了优势. |
| first_indexed | 2024-04-24T17:02:02Z |
| format | Article |
| id | doaj.art-08995b1e8f9c4802967bd4b2b2399b35 |
| institution | Directory Open Access Journal |
| issn | 1008-9497 |
| language | zho |
| last_indexed | 2024-04-24T17:02:02Z |
| publishDate | 2003-09-01 |
| publisher | Zhejiang University Press |
| record_format | Article |
| series | Zhejiang Daxue xuebao. Lixue ban |
| spelling | doaj.art-08995b1e8f9c4802967bd4b2b2399b352024-03-29T01:58:20ZzhoZhejiang University PressZhejiang Daxue xuebao. Lixue ban1008-94972003-09-01305518523zjup/1008-9497.2003.30.5.518-523Tabular synthesis of three-variable functions using one-bit full adders(基于一位全加器三变量逻辑函数的查表综合)ZHOUChang(周畅)0WUYin-er(伍银儿)1CHENXie-xiong(陈偕雄)2Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310028, China(浙江大学信息与电子工程系，浙江 杭州 310028)Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310028, China(浙江大学信息与电子工程系，浙江 杭州 310028)Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310028, China(浙江大学信息与电子工程系，浙江 杭州 310028)通过对1个一位全加器3个输入端不同的组合,可以实现与门、或门、非门、同或门及异或门,因此全加器在数字逻辑电路中有着重要的作用.本文在介绍全加器的基础上提出了用查表法设计基于一位全加器实现任意三变量函数的组合电路和时序电路.在与传统的与非门/或非门的比较中,它显示了优势.https://doi.org/zjup/1008-9497.2003.30.5.518-523全加器逻辑综合对称函数函数分类vlsilsi触发器 |
| spellingShingle | ZHOUChang(周畅) WUYin-er(伍银儿) CHENXie-xiong(陈偕雄) Tabular synthesis of three-variable functions using one-bit full adders(基于一位全加器三变量逻辑函数的查表综合) Zhejiang Daxue xuebao. Lixue ban 全加器 逻辑综合 对称函数 函数分类 vlsi lsi 触发器 |
| title | Tabular synthesis of three-variable functions using one-bit full adders(基于一位全加器三变量逻辑函数的查表综合) |
| title_full | Tabular synthesis of three-variable functions using one-bit full adders(基于一位全加器三变量逻辑函数的查表综合) |
| title_fullStr | Tabular synthesis of three-variable functions using one-bit full adders(基于一位全加器三变量逻辑函数的查表综合) |
| title_full_unstemmed | Tabular synthesis of three-variable functions using one-bit full adders(基于一位全加器三变量逻辑函数的查表综合) |
| title_short | Tabular synthesis of three-variable functions using one-bit full adders(基于一位全加器三变量逻辑函数的查表综合) |
| title_sort | tabular synthesis of three variable functions using one bit full adders 基于一位全加器三变量逻辑函数的查表综合 |
| topic | 全加器 逻辑综合 对称函数 函数分类 vlsi lsi 触发器 |
| url | https://doi.org/zjup/1008-9497.2003.30.5.518-523 |
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