A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization
Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compar...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/15/1791 |
| _version_ | 1797525691669938176 |
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| author | Muhammad Ali Akbar Bo Wang Amine Bermak |
| author_facet | Muhammad Ali Akbar Bo Wang Amine Bermak |
| author_sort | Muhammad Ali Akbar |
| collection | DOAJ |
| description | Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design. |
| first_indexed | 2024-03-10T09:16:39Z |
| format | Article |
| id | doaj.art-08c77075cf964a60ac0fec828915ee54 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T09:16:39Z |
| publishDate | 2021-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-08c77075cf964a60ac0fec828915ee542023-11-22T05:30:58ZengMDPI AGElectronics2079-92922021-07-011015179110.3390/electronics10151791A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and LocalizationMuhammad Ali Akbar0Bo Wang1Amine Bermak2Division of Information and Computing Technology, College of Science and Engineering, Hamad Bin Khalifa University, Doha 34110, QatarDivision of Information and Computing Technology, College of Science and Engineering, Hamad Bin Khalifa University, Doha 34110, QatarDivision of Information and Computing Technology, College of Science and Engineering, Hamad Bin Khalifa University, Doha 34110, QatarRipple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design.https://www.mdpi.com/2079-9292/10/15/1791fast adderhybrid adderripple carry adderself-checking |
| spellingShingle | Muhammad Ali Akbar Bo Wang Amine Bermak A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization Electronics fast adder hybrid adder ripple carry adder self-checking |
| title | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_full | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_fullStr | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_full_unstemmed | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_short | A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization |
| title_sort | high speed parallel architecture for ripple carry adder with fault detection and localization |
| topic | fast adder hybrid adder ripple carry adder self-checking |
| url | https://www.mdpi.com/2079-9292/10/15/1791 |
| work_keys_str_mv | AT muhammadaliakbar ahighspeedparallelarchitectureforripplecarryadderwithfaultdetectionandlocalization AT bowang ahighspeedparallelarchitectureforripplecarryadderwithfaultdetectionandlocalization AT aminebermak ahighspeedparallelarchitectureforripplecarryadderwithfaultdetectionandlocalization AT muhammadaliakbar highspeedparallelarchitectureforripplecarryadderwithfaultdetectionandlocalization AT bowang highspeedparallelarchitectureforripplecarryadderwithfaultdetectionandlocalization AT aminebermak highspeedparallelarchitectureforripplecarryadderwithfaultdetectionandlocalization |