A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center Communication
A novel pole-tuning technique with T-type network for interstage bandwidth extension is proposed in this paper. By exploiting the proposed technique in interstage of amplifiers, the transfer function of each stage exhibits two dominant poles, achieving a flat gain-frequency response over an ultrawid...
| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2018-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8468147/ |
| _version_ | 1819163080416821248 |
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| author | Jiang Luo Jin He Guangyin Feng Alit Apriyana Ya Fang Zhe Xue Qijun Huang Hao Yu |
| author_facet | Jiang Luo Jin He Guangyin Feng Alit Apriyana Ya Fang Zhe Xue Qijun Huang Hao Yu |
| author_sort | Jiang Luo |
| collection | DOAJ |
| description | A novel pole-tuning technique with T-type network for interstage bandwidth extension is proposed in this paper. By exploiting the proposed technique in interstage of amplifiers, the transfer function of each stage exhibits two dominant poles, achieving a flat gain-frequency response over an ultrawide bandwidth. For verification, a four-stage amplifier based on the pole-tuning technique with T-type network has been designed and implemented in a 65-nm bulk CMOS technology. The fabricated prototype achieves a peak gain of 9.5 dB at 122 GHz with a 3-dB bandwidth of more than 26 GHz and a fractional bandwidth of larger than 21.3%, while consuming a dc power of 62 mW. At the operating frequency of 125 GHz, the saturation output power and the output P<sub>1 dB</sub> are 8.6 and 4.6 dBm, respectively. The chip occupies a small silicon area of 0.27 mm<sup>2</sup> including all testing pads with a core size of only 0.105 mm<sup>2</sup>. The proposed amplifier is suitable for short-distance data center communication as one of the key building blocks. |
| first_indexed | 2024-12-22T17:38:27Z |
| format | Article |
| id | doaj.art-095cc0539d9d4e93802c278e62a4960e |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-22T17:38:27Z |
| publishDate | 2018-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-095cc0539d9d4e93802c278e62a4960e2022-12-21T18:18:27ZengIEEEIEEE Access2169-35362018-01-016531915320010.1109/ACCESS.2018.28710478468147A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center CommunicationJiang Luo0https://orcid.org/0000-0003-4519-792XJin He1https://orcid.org/0000-0002-8747-0472Guangyin Feng2Alit Apriyana3Ya Fang4Zhe Xue5Qijun Huang6Hao Yu7School of Physics and Technology, Wuhan University, Wuhan, ChinaSchool of Physics and Technology, Wuhan University, Wuhan, ChinaSchool of Electrical and Electronic Engineering, Nanyang Technological University, SingaporeSchool of Electrical and Electronic Engineering, Nanyang Technological University, SingaporeSchool of Physics and Technology, Wuhan University, Wuhan, ChinaSchool of Physics and Technology, Wuhan University, Wuhan, ChinaSchool of Physics and Technology, Wuhan University, Wuhan, ChinaDepartment of Electrical and Electronic Engineering, Southern University of Science and Technology, Shenzhen, ChinaA novel pole-tuning technique with T-type network for interstage bandwidth extension is proposed in this paper. By exploiting the proposed technique in interstage of amplifiers, the transfer function of each stage exhibits two dominant poles, achieving a flat gain-frequency response over an ultrawide bandwidth. For verification, a four-stage amplifier based on the pole-tuning technique with T-type network has been designed and implemented in a 65-nm bulk CMOS technology. The fabricated prototype achieves a peak gain of 9.5 dB at 122 GHz with a 3-dB bandwidth of more than 26 GHz and a fractional bandwidth of larger than 21.3%, while consuming a dc power of 62 mW. At the operating frequency of 125 GHz, the saturation output power and the output P<sub>1 dB</sub> are 8.6 and 4.6 dBm, respectively. The chip occupies a small silicon area of 0.27 mm<sup>2</sup> including all testing pads with a core size of only 0.105 mm<sup>2</sup>. The proposed amplifier is suitable for short-distance data center communication as one of the key building blocks.https://ieeexplore.ieee.org/document/8468147/CMOSmillimeter-wave (mm-wave)broadband amplifiersbandwidth extensionT-type networkpole-tuning |
| spellingShingle | Jiang Luo Jin He Guangyin Feng Alit Apriyana Ya Fang Zhe Xue Qijun Huang Hao Yu A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center Communication IEEE Access CMOS millimeter-wave (mm-wave) broadband amplifiers bandwidth extension T-type network pole-tuning |
| title | A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center Communication |
| title_full | A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center Communication |
| title_fullStr | A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center Communication |
| title_full_unstemmed | A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center Communication |
| title_short | A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center Communication |
| title_sort | d band amplifier in 65 nm bulk cmos for short distance data center communication |
| topic | CMOS millimeter-wave (mm-wave) broadband amplifiers bandwidth extension T-type network pole-tuning |
| url | https://ieeexplore.ieee.org/document/8468147/ |
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