PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation
Abstract This paper deals with the design and implementation of the conventional Level‐Shifted‐PWM (LS‐PWM) and the PWM‐hybrid modulation techniques in a Field‐Programmable Gate Array (FPGA) development card, applicable to binary asymmetric multilevel converters; particularly herein, the Binary‐Asym...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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Wiley
2021-06-01
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| Series: | IET Power Electronics |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/pel2.12131 |
| _version_ | 1811246020882857984 |
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| author | José A. Juárez‐Abad Jorge L. Barahona‐Avalos Jesús Linares‐Flores |
| author_facet | José A. Juárez‐Abad Jorge L. Barahona‐Avalos Jesús Linares‐Flores |
| author_sort | José A. Juárez‐Abad |
| collection | DOAJ |
| description | Abstract This paper deals with the design and implementation of the conventional Level‐Shifted‐PWM (LS‐PWM) and the PWM‐hybrid modulation techniques in a Field‐Programmable Gate Array (FPGA) development card, applicable to binary asymmetric multilevel converters; particularly herein, the Binary‐Asymmetric Cascade Multilevel Inverter is treated (B‐ACMLI). We employ an FPGA‐based switching‐controller to provide pulses for Multilevel Inverter (MLI) power semiconductors via their gate‐drivers. The modulation strategies were implemented via an FPGA with a 32‐bit floating‐point architecture considering the IEEE‐754 standard's recommendations. The portability of the design is ensured using VHDL . The use of embedded RAM blocks minimizes the logical resources consumed into the FPGA, increases overall speed, and reduces power consumption. A comparison is presented in terms of the number of resources used in both modulation techniques. A low‐cost FPGA board named Pipistrello is used. Pipistrello is an FPGA development board for Xilinx Spartan‐6 LX45, designed by Saanlima Electronics. The platform consisting of a single‐phase seven‐level inverter B‐ACMLI hardware prototype. The experimental results show the effectiveness of the approach. As isolated voltage‐sources, photovoltaic modules are used for the experimental setup to the B‐ACMLI. |
| first_indexed | 2024-04-12T14:47:39Z |
| format | Article |
| id | doaj.art-0caf48e0292646c8af258199707e9826 |
| institution | Directory Open Access Journal |
| issn | 1755-4535 1755-4543 |
| language | English |
| last_indexed | 2024-04-12T14:47:39Z |
| publishDate | 2021-06-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Power Electronics |
| spelling | doaj.art-0caf48e0292646c8af258199707e98262022-12-22T03:28:36ZengWileyIET Power Electronics1755-45351755-45432021-06-011481529153910.1049/pel2.12131PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementationJosé A. Juárez‐Abad0Jorge L. Barahona‐Avalos1Jesús Linares‐Flores2Instituto de Electrónica y Mecatrónica Universidad Tecnológica de la Mixteca Huajuapan de León Oaxaca MéxicoInstituto de Electrónica y Mecatrónica Universidad Tecnológica de la Mixteca Huajuapan de León Oaxaca MéxicoInstituto de Electrónica y Mecatrónica Universidad Tecnológica de la Mixteca Huajuapan de León Oaxaca MéxicoAbstract This paper deals with the design and implementation of the conventional Level‐Shifted‐PWM (LS‐PWM) and the PWM‐hybrid modulation techniques in a Field‐Programmable Gate Array (FPGA) development card, applicable to binary asymmetric multilevel converters; particularly herein, the Binary‐Asymmetric Cascade Multilevel Inverter is treated (B‐ACMLI). We employ an FPGA‐based switching‐controller to provide pulses for Multilevel Inverter (MLI) power semiconductors via their gate‐drivers. The modulation strategies were implemented via an FPGA with a 32‐bit floating‐point architecture considering the IEEE‐754 standard's recommendations. The portability of the design is ensured using VHDL . The use of embedded RAM blocks minimizes the logical resources consumed into the FPGA, increases overall speed, and reduces power consumption. A comparison is presented in terms of the number of resources used in both modulation techniques. A low‐cost FPGA board named Pipistrello is used. Pipistrello is an FPGA development board for Xilinx Spartan‐6 LX45, designed by Saanlima Electronics. The platform consisting of a single‐phase seven‐level inverter B‐ACMLI hardware prototype. The experimental results show the effectiveness of the approach. As isolated voltage‐sources, photovoltaic modules are used for the experimental setup to the B‐ACMLI.https://doi.org/10.1049/pel2.12131Power electronics, supply and supervisory circuitsDigital circuit design, modelling and testingLogic circuitsDC‐AC power convertors (invertors) |
| spellingShingle | José A. Juárez‐Abad Jorge L. Barahona‐Avalos Jesús Linares‐Flores PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation IET Power Electronics Power electronics, supply and supervisory circuits Digital circuit design, modelling and testing Logic circuits DC‐AC power convertors (invertors) |
| title | PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation |
| title_full | PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation |
| title_fullStr | PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation |
| title_full_unstemmed | PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation |
| title_short | PWM techniques for an asymmetric multilevel binary inverter: an FPGA‐based implementation |
| title_sort | pwm techniques for an asymmetric multilevel binary inverter an fpga based implementation |
| topic | Power electronics, supply and supervisory circuits Digital circuit design, modelling and testing Logic circuits DC‐AC power convertors (invertors) |
| url | https://doi.org/10.1049/pel2.12131 |
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