Accelerating SuperBE with Hardware/Software Co-Design
Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce over...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2018-10-01
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| Series: | Journal of Imaging |
| Subjects: | |
| Online Access: | http://www.mdpi.com/2313-433X/4/10/122 |
| _version_ | 1818317409654669312 |
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| author | Andrew Tzer-Yeu Chen Rohaan Gupta Anton Borzenko Kevin I-Kai Wang Morteza Biglari-Abhari |
| author_facet | Andrew Tzer-Yeu Chen Rohaan Gupta Anton Borzenko Kevin I-Kai Wang Morteza Biglari-Abhari |
| author_sort | Andrew Tzer-Yeu Chen |
| collection | DOAJ |
| description | Background Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for simplicity and reducing computational complexity while maintaining state-of-the-art levels of accuracy. We explore both software and hardware acceleration opportunities, converting the original algorithm into a greyscale, integer-only version, and using Hardware/Software Co-design to develop hardware acceleration components on FPGA fabric that assist a software processor. We achieved a 4.4× speed improvement with the software optimisations alone, and a 2× speed improvement with the hardware optimisations alone. When combined, these led to a 9× speed improvement on a Cyclone V System-on-Chip, delivering almost 38 fps on 320 × 240 resolution images. |
| first_indexed | 2024-12-13T09:36:52Z |
| format | Article |
| id | doaj.art-0d49b6853f6644f1acb22537aa43edb8 |
| institution | Directory Open Access Journal |
| issn | 2313-433X |
| language | English |
| last_indexed | 2024-12-13T09:36:52Z |
| publishDate | 2018-10-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Imaging |
| spelling | doaj.art-0d49b6853f6644f1acb22537aa43edb82022-12-21T23:52:18ZengMDPI AGJournal of Imaging2313-433X2018-10-0141012210.3390/jimaging4100122jimaging4100122Accelerating SuperBE with Hardware/Software Co-DesignAndrew Tzer-Yeu Chen0Rohaan Gupta1Anton Borzenko2Kevin I-Kai Wang3Morteza Biglari-Abhari4Embedded Systems Research Group, Department of Electrical and Computer Engineering, The University of Auckland, Auckland 1023, New ZealandEmbedded Systems Research Group, Department of Electrical and Computer Engineering, The University of Auckland, Auckland 1023, New ZealandEmbedded Systems Research Group, Department of Electrical and Computer Engineering, The University of Auckland, Auckland 1023, New ZealandEmbedded Systems Research Group, Department of Electrical and Computer Engineering, The University of Auckland, Auckland 1023, New ZealandEmbedded Systems Research Group, Department of Electrical and Computer Engineering, The University of Auckland, Auckland 1023, New ZealandBackground Estimation is a common computer vision task, used for segmenting moving objects in video streams. This can be useful as a pre-processing step, isolating regions of interest for more complicated algorithms performing detection, recognition, and identification tasks, in order to reduce overall computation time. This is especially important in the context of embedded systems like smart cameras, which may need to process images with constrained computational resources. This work focuses on accelerating SuperBE, a superpixel-based background estimation algorithm that was designed for simplicity and reducing computational complexity while maintaining state-of-the-art levels of accuracy. We explore both software and hardware acceleration opportunities, converting the original algorithm into a greyscale, integer-only version, and using Hardware/Software Co-design to develop hardware acceleration components on FPGA fabric that assist a software processor. We achieved a 4.4× speed improvement with the software optimisations alone, and a 2× speed improvement with the hardware optimisations alone. When combined, these led to a 9× speed improvement on a Cyclone V System-on-Chip, delivering almost 38 fps on 320 × 240 resolution images.http://www.mdpi.com/2313-433X/4/10/122background estimationimage segmentationSystem-on-Chipembedded systemsreal-time systemshardware accelerators |
| spellingShingle | Andrew Tzer-Yeu Chen Rohaan Gupta Anton Borzenko Kevin I-Kai Wang Morteza Biglari-Abhari Accelerating SuperBE with Hardware/Software Co-Design Journal of Imaging background estimation image segmentation System-on-Chip embedded systems real-time systems hardware accelerators |
| title | Accelerating SuperBE with Hardware/Software Co-Design |
| title_full | Accelerating SuperBE with Hardware/Software Co-Design |
| title_fullStr | Accelerating SuperBE with Hardware/Software Co-Design |
| title_full_unstemmed | Accelerating SuperBE with Hardware/Software Co-Design |
| title_short | Accelerating SuperBE with Hardware/Software Co-Design |
| title_sort | accelerating superbe with hardware software co design |
| topic | background estimation image segmentation System-on-Chip embedded systems real-time systems hardware accelerators |
| url | http://www.mdpi.com/2313-433X/4/10/122 |
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