An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications
Currently, dynamic comparator approach necessitates in high-speed and power efficient analog-to-digital converter applications due to its high latching speed and ultra-low power consumption. In this paper, a~novel dynamic comparator is proposed to reduce latch delay and offset. The comparator benefi...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
VSB-Technical University of Ostrava
2019-01-01
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| Series: | Advances in Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://advances.utc.sk/index.php/AEEE/article/view/3326 |
| _version_ | 1797826945589706752 |
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| author | Vikrant Varshney Rajendra Kumar Nagaria |
| author_facet | Vikrant Varshney Rajendra Kumar Nagaria |
| author_sort | Vikrant Varshney |
| collection | DOAJ |
| description | Currently, dynamic comparator approach necessitates in high-speed and power efficient analog-to-digital converter applications due to its high latching speed and ultra-low power consumption. In this paper, a~novel dynamic comparator is proposed to reduce latch delay and offset. The comparator benefits from add-on cross-coupled transistors in latch structure and unbalanced clocks to enhance comparison speed and to lessen input offset voltage occurred due to mismatch in cross-coupled circuits in latch stage. The derivations for delay and input offset voltage are presented for proposed dynamic comparator with meticulous Monte-Carlo simulations. The results are verified by simulations in CADENCE SPECTRE at 1V supply voltage and 90nm CMOS technology. A~comparative analysis between the proposed dynamic comparator and the previous reported comparators has been presented. It is observed that the delay is reduced up to 46% and 6% as compared to conventional and two phase dynamic comparator, respectively. Moreover, the proposed design consumes 53.36muW power only. The Monte-Carlo simulation shows that the standard deviation of input offset voltage is 10.8~mV which is 12% and 77% of conventional and two phase dynamic comparator, respectively. |
| first_indexed | 2024-04-09T12:40:25Z |
| format | Article |
| id | doaj.art-0f2575ebf7f145cbb86748f84952b843 |
| institution | Directory Open Access Journal |
| issn | 1336-1376 1804-3119 |
| language | English |
| last_indexed | 2024-04-09T12:40:25Z |
| publishDate | 2019-01-01 |
| publisher | VSB-Technical University of Ostrava |
| record_format | Article |
| series | Advances in Electrical and Electronic Engineering |
| spelling | doaj.art-0f2575ebf7f145cbb86748f84952b8432023-05-14T20:50:13ZengVSB-Technical University of OstravaAdvances in Electrical and Electronic Engineering1336-13761804-31192019-01-0117444645810.15598/aeee.v17i4.33261070An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC ApplicationsVikrant Varshney0Rajendra Kumar Nagaria1Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology, MNNIT Allahabad Campus, Teliarganj, Allahabad, 211004 Uttar Pradesh, IndiaDepartment of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology, MNNIT Allahabad Campus, Teliarganj, Allahabad, 211004 Uttar Pradesh, IndiaCurrently, dynamic comparator approach necessitates in high-speed and power efficient analog-to-digital converter applications due to its high latching speed and ultra-low power consumption. In this paper, a~novel dynamic comparator is proposed to reduce latch delay and offset. The comparator benefits from add-on cross-coupled transistors in latch structure and unbalanced clocks to enhance comparison speed and to lessen input offset voltage occurred due to mismatch in cross-coupled circuits in latch stage. The derivations for delay and input offset voltage are presented for proposed dynamic comparator with meticulous Monte-Carlo simulations. The results are verified by simulations in CADENCE SPECTRE at 1V supply voltage and 90nm CMOS technology. A~comparative analysis between the proposed dynamic comparator and the previous reported comparators has been presented. It is observed that the delay is reduced up to 46% and 6% as compared to conventional and two phase dynamic comparator, respectively. Moreover, the proposed design consumes 53.36muW power only. The Monte-Carlo simulation shows that the standard deviation of input offset voltage is 10.8~mV which is 12% and 77% of conventional and two phase dynamic comparator, respectively.http://advances.utc.sk/index.php/AEEE/article/view/3326dynamic comparatorhigh speedlatch comparatorlow offset designunbalanced clock. |
| spellingShingle | Vikrant Varshney Rajendra Kumar Nagaria An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications Advances in Electrical and Electronic Engineering dynamic comparator high speed latch comparator low offset design unbalanced clock. |
| title | An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications |
| title_full | An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications |
| title_fullStr | An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications |
| title_full_unstemmed | An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications |
| title_short | An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications |
| title_sort | unbalanced clock based dynamic comparator a high speed low offset design approach for adc applications |
| topic | dynamic comparator high speed latch comparator low offset design unbalanced clock. |
| url | http://advances.utc.sk/index.php/AEEE/article/view/3326 |
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