Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends
This paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before r...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2024-02-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/15/2/247 |
| _version_ | 1797297451352195072 |
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| author | Marcian Cirstea Khaled Benkrid Andrei Dinu Romeo Ghiriti Dorin Petreus |
| author_facet | Marcian Cirstea Khaled Benkrid Andrei Dinu Romeo Ghiriti Dorin Petreus |
| author_sort | Marcian Cirstea |
| collection | DOAJ |
| description | This paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before reviewing SoC design methodologies and tools. The fundamentals of SoC design flows are laid out. The paper then exposes the crucial role of the intellectual property (IP) industry in the relentless improvements in performance, power, area, and cost (PPAC) attributes of SoCs. High abstraction levels in design capture and increasingly automated design tools (e.g., for verification and validation, synthesis, place, and route) continue to push the boundaries. Aerospace and automotive domains are included as brief case studies. This paper also presents current and future trends in SoC design and implementation including the rising, evolution, and usage of machine learning (ML) and artificial intelligence (AI) algorithms, techniques, and tools, which promise even greater PPAC optimizations. |
| first_indexed | 2024-03-07T22:20:30Z |
| format | Article |
| id | doaj.art-0f7312a8f575418cb52ac33c36b6bd51 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-07T22:20:30Z |
| publishDate | 2024-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-0f7312a8f575418cb52ac33c36b6bd512024-02-23T15:27:46ZengMDPI AGMicromachines2072-666X2024-02-0115224710.3390/mi15020247Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and TrendsMarcian Cirstea0Khaled Benkrid1Andrei Dinu2Romeo Ghiriti3Dorin Petreus4School of Computing and Information Science, Anglia Ruskin University, East Road, Cambridge CB1 1PT, UKArm Ltd., 110 Fulbourn Rd, Cambridge CB1 9NJ, UKCollins Aerospace, Fore 3, Huskisson Way, Stratford Road, Shirley B90 4SS, UKExquisite IT Ltd., 33 Stokes Drive, Huntingdon PE29 2UW, UKApplied Electronics Department, Technical University of Cluj-Napoca, Baritiu Street, 400027 Cluj-Napoca, RomaniaThis paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before reviewing SoC design methodologies and tools. The fundamentals of SoC design flows are laid out. The paper then exposes the crucial role of the intellectual property (IP) industry in the relentless improvements in performance, power, area, and cost (PPAC) attributes of SoCs. High abstraction levels in design capture and increasingly automated design tools (e.g., for verification and validation, synthesis, place, and route) continue to push the boundaries. Aerospace and automotive domains are included as brief case studies. This paper also presents current and future trends in SoC design and implementation including the rising, evolution, and usage of machine learning (ML) and artificial intelligence (AI) algorithms, techniques, and tools, which promise even greater PPAC optimizations.https://www.mdpi.com/2072-666X/15/2/247system-on-chip (SoC)design methodologyfield programmable gate array (FPGA)electronic design automation (EDA)electronic system level (ESL) designhigh level synthesis (HLS) |
| spellingShingle | Marcian Cirstea Khaled Benkrid Andrei Dinu Romeo Ghiriti Dorin Petreus Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends Micromachines system-on-chip (SoC) design methodology field programmable gate array (FPGA) electronic design automation (EDA) electronic system level (ESL) design high level synthesis (HLS) |
| title | Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends |
| title_full | Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends |
| title_fullStr | Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends |
| title_full_unstemmed | Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends |
| title_short | Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends |
| title_sort | digital electronic system on chip design methodologies tools evolution and trends |
| topic | system-on-chip (SoC) design methodology field programmable gate array (FPGA) electronic design automation (EDA) electronic system level (ESL) design high level synthesis (HLS) |
| url | https://www.mdpi.com/2072-666X/15/2/247 |
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