Serial RRAM Cell for Secure Bit Concealing
Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. Thi...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/15/1842 |
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| author | Binbin Yang Daniel Arumí Salvador Manich Álvaro Gómez-Pau Rosa Rodríguez-Montañés Mireia Bargalló González Francesca Campabadal Liang Fang |
| author_facet | Binbin Yang Daniel Arumí Salvador Manich Álvaro Gómez-Pau Rosa Rodríguez-Montañés Mireia Bargalló González Francesca Campabadal Liang Fang |
| author_sort | Binbin Yang |
| collection | DOAJ |
| description | Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal. |
| first_indexed | 2024-03-10T09:16:40Z |
| format | Article |
| id | doaj.art-0fa7a793b3ef46eebd0d7431c8e0dd4b |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T09:16:40Z |
| publishDate | 2021-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-0fa7a793b3ef46eebd0d7431c8e0dd4b2023-11-22T05:31:45ZengMDPI AGElectronics2079-92922021-07-011015184210.3390/electronics10151842Serial RRAM Cell for Secure Bit ConcealingBinbin Yang0Daniel Arumí1Salvador Manich2Álvaro Gómez-Pau3Rosa Rodríguez-Montañés4Mireia Bargalló González5Francesca Campabadal6Liang Fang7Institute for Quantum Information & State Key Laboratory of High Performance Computing, College of Computer, National University of Defense Technology, Changsha 410073, ChinaDepartament d’Enginyeria Electrònica, Universitat Politècnica de Catalunya, 08028 Barcelona, SpainDepartament d’Enginyeria Electrònica, Universitat Politècnica de Catalunya, 08028 Barcelona, SpainDepartament d’Enginyeria Electrònica, Universitat Politècnica de Catalunya, 08028 Barcelona, SpainDepartament d’Enginyeria Electrònica, Universitat Politècnica de Catalunya, 08028 Barcelona, SpainInstitut de Microelectrònica de Barcelona-Centre Nacional de Microelectrònica, Consejo Superior de Investigaciones Científicas, 08193 Bellaterra, SpainInstitut de Microelectrònica de Barcelona-Centre Nacional de Microelectrònica, Consejo Superior de Investigaciones Científicas, 08193 Bellaterra, SpainInstitute for Quantum Information & State Key Laboratory of High Performance Computing, College of Computer, National University of Defense Technology, Changsha 410073, ChinaNon-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal.https://www.mdpi.com/2079-9292/10/15/1842RRAMsecure non-volatile memoriesvariabilitymaskinghardware security |
| spellingShingle | Binbin Yang Daniel Arumí Salvador Manich Álvaro Gómez-Pau Rosa Rodríguez-Montañés Mireia Bargalló González Francesca Campabadal Liang Fang Serial RRAM Cell for Secure Bit Concealing Electronics RRAM secure non-volatile memories variability masking hardware security |
| title | Serial RRAM Cell for Secure Bit Concealing |
| title_full | Serial RRAM Cell for Secure Bit Concealing |
| title_fullStr | Serial RRAM Cell for Secure Bit Concealing |
| title_full_unstemmed | Serial RRAM Cell for Secure Bit Concealing |
| title_short | Serial RRAM Cell for Secure Bit Concealing |
| title_sort | serial rram cell for secure bit concealing |
| topic | RRAM secure non-volatile memories variability masking hardware security |
| url | https://www.mdpi.com/2079-9292/10/15/1842 |
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