Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning
In this paper, we propose a floating-gate-based synaptic transistor with two independent control gates that implement both offline and online learning. Unlike previous research on double-gated synaptic transistors, the proposed device is capable of online learning without facing a fan-out problem. B...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9274391/ |
| _version_ | 1818874211738845184 |
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| author | Donghyun Ryu Tae-Hyung Kim Taejin Jang Junsu Yu Jong-Ho Lee Byung-Gook Park |
| author_facet | Donghyun Ryu Tae-Hyung Kim Taejin Jang Junsu Yu Jong-Ho Lee Byung-Gook Park |
| author_sort | Donghyun Ryu |
| collection | DOAJ |
| description | In this paper, we propose a floating-gate-based synaptic transistor with two independent control gates that implement both offline and online learning. Unlike previous research on double-gated synaptic transistors, the proposed device is capable of online learning without facing a fan-out problem. Basic operation of the device was verified and a program/erase scheme based on Fowler-Northeim tunneling is suggested for the multi-conductance utilization of the synaptic device. With the proposed P/E scheme, an offline-trained single-layered hardware-based spiking neural network was simulated for MNIST classification, resulting in 87.37% classification accuracy with 10% conductance variation. To alleviate this performance degradation, the online learning method is applied on the offline-trained SNN by reusing 3,000 training images. The effectiveness of the proposed method is also verified under existence of the synaptic weight variance. As a result, up to 86.89% of the performance degradation is alleviated. |
| first_indexed | 2024-12-19T13:07:00Z |
| format | Article |
| id | doaj.art-103d620caea54b99bea562ba522f487d |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-19T13:07:00Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-103d620caea54b99bea562ba522f487d2022-12-21T20:20:01ZengIEEEIEEE Access2169-35362020-01-01821773521774310.1109/ACCESS.2020.30417349274391Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online LearningDonghyun Ryu0https://orcid.org/0000-0002-5800-7251Tae-Hyung Kim1Taejin Jang2Junsu Yu3https://orcid.org/0000-0002-2746-0213Jong-Ho Lee4https://orcid.org/0000-0003-3559-9802Byung-Gook Park5https://orcid.org/0000-0002-2962-2458Inter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaInter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaInter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaInter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaInter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaInter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South KoreaIn this paper, we propose a floating-gate-based synaptic transistor with two independent control gates that implement both offline and online learning. Unlike previous research on double-gated synaptic transistors, the proposed device is capable of online learning without facing a fan-out problem. Basic operation of the device was verified and a program/erase scheme based on Fowler-Northeim tunneling is suggested for the multi-conductance utilization of the synaptic device. With the proposed P/E scheme, an offline-trained single-layered hardware-based spiking neural network was simulated for MNIST classification, resulting in 87.37% classification accuracy with 10% conductance variation. To alleviate this performance degradation, the online learning method is applied on the offline-trained SNN by reusing 3,000 training images. The effectiveness of the proposed method is also verified under existence of the synaptic weight variance. As a result, up to 86.89% of the performance degradation is alleviated.https://ieeexplore.ieee.org/document/9274391/CMOSflash memorysynaptic deviceneuromorphic systemoffline learningonline learning |
| spellingShingle | Donghyun Ryu Tae-Hyung Kim Taejin Jang Junsu Yu Jong-Ho Lee Byung-Gook Park Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning IEEE Access CMOS flash memory synaptic device neuromorphic system offline learning online learning |
| title | Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning |
| title_full | Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning |
| title_fullStr | Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning |
| title_full_unstemmed | Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning |
| title_short | Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning |
| title_sort | double gated asymmetric floating gate based synaptic device for effective performance enhancement through online learning |
| topic | CMOS flash memory synaptic device neuromorphic system offline learning online learning |
| url | https://ieeexplore.ieee.org/document/9274391/ |
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