Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller
This paper presents an innovative approach for predicting timing errors tailored to near-/sub-threshold operations, addressing the energy-efficient requirements of digital circuits in applications, such as IoT devices and wearables. The method involves assessing deep path activity within an adjustab...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-08-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/23/17/7498 |
| _version_ | 1797581823768788992 |
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| author | Run-Ze Yu Zhen-Hao Li Xi Deng Zheng-Lin Liu |
| author_facet | Run-Ze Yu Zhen-Hao Li Xi Deng Zheng-Lin Liu |
| author_sort | Run-Ze Yu |
| collection | DOAJ |
| description | This paper presents an innovative approach for predicting timing errors tailored to near-/sub-threshold operations, addressing the energy-efficient requirements of digital circuits in applications, such as IoT devices and wearables. The method involves assessing deep path activity within an adjustable window prior to the root clock’s rising edge. By dynamically adapting the prediction window and supply voltage based on error detection outcomes, the approach effectively mitigates false predictions—an essential concern in low-voltage prediction techniques. The efficacy of this strategy is demonstrated through its implementation in a near-/sub-threshold 32-bit microprocessor system. The approach incurs only a modest 6.84% area overhead attributed to well-engineered lightweight design methodologies. Furthermore, with the integration of clock gating, the system functions seamlessly across a voltage range of 0.4 V–1.2 V (5–100 MHz), effectively catering to adaptive energy efficiency. Empirical results highlight the potential of the proposed strategy, achieving a significant 46.95% energy reduction at the Minimum Energy Point (MEP, 15 MHz) compared to signoff margins. Additionally, a 19.75% energy decrease is observed compared to the zero-margin operation, demonstrating successful realization of negative margins. |
| first_indexed | 2024-03-10T23:13:02Z |
| format | Article |
| id | doaj.art-1060c2b4e6c64d4b8022c4357b020fda |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-10T23:13:02Z |
| publishDate | 2023-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-1060c2b4e6c64d4b8022c4357b020fda2023-11-19T08:50:41ZengMDPI AGSensors1424-82202023-08-012317749810.3390/s23177498Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit MicrocontrollerRun-Ze Yu0Zhen-Hao Li1Xi Deng2Zheng-Lin Liu3School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, ChinaSchool of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, ChinaThis paper presents an innovative approach for predicting timing errors tailored to near-/sub-threshold operations, addressing the energy-efficient requirements of digital circuits in applications, such as IoT devices and wearables. The method involves assessing deep path activity within an adjustable window prior to the root clock’s rising edge. By dynamically adapting the prediction window and supply voltage based on error detection outcomes, the approach effectively mitigates false predictions—an essential concern in low-voltage prediction techniques. The efficacy of this strategy is demonstrated through its implementation in a near-/sub-threshold 32-bit microprocessor system. The approach incurs only a modest 6.84% area overhead attributed to well-engineered lightweight design methodologies. Furthermore, with the integration of clock gating, the system functions seamlessly across a voltage range of 0.4 V–1.2 V (5–100 MHz), effectively catering to adaptive energy efficiency. Empirical results highlight the potential of the proposed strategy, achieving a significant 46.95% energy reduction at the Minimum Energy Point (MEP, 15 MHz) compared to signoff margins. Additionally, a 19.75% energy decrease is observed compared to the zero-margin operation, demonstrating successful realization of negative margins.https://www.mdpi.com/1424-8220/23/17/7498dynamic voltage scaling (DVS)negative design marginerror detection and correction (EDaC)ultra-low voltagenear-threshold operationhigh stability |
| spellingShingle | Run-Ze Yu Zhen-Hao Li Xi Deng Zheng-Lin Liu Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller Sensors dynamic voltage scaling (DVS) negative design margin error detection and correction (EDaC) ultra-low voltage near-threshold operation high stability |
| title | Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller |
| title_full | Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller |
| title_fullStr | Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller |
| title_full_unstemmed | Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller |
| title_short | Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller |
| title_sort | negative design margin realization through deep path activity detection combined with dynamic voltage scaling in a 55 nm near threshold 32 bit microcontroller |
| topic | dynamic voltage scaling (DVS) negative design margin error detection and correction (EDaC) ultra-low voltage near-threshold operation high stability |
| url | https://www.mdpi.com/1424-8220/23/17/7498 |
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