ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices
IoT edge devices process the data collected, which can contain sensitive information related to the user. It is crucial to incorporate robust encryption algorithms considering the resource and power budget of these devices. In this paper, we present a power-based SCA-resistant implementation of the...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9645047/ |
| _version_ | 1819282255037595648 |
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| author | M. Aamir Somya Sharma Anuj Grover |
| author_facet | M. Aamir Somya Sharma Anuj Grover |
| author_sort | M. Aamir |
| collection | DOAJ |
| description | IoT edge devices process the data collected, which can contain sensitive information related to the user. It is crucial to incorporate robust encryption algorithms considering the resource and power budget of these devices. In this paper, we present a power-based SCA-resistant implementation of the ChaCha20 encryption algorithm for low-end devices by utilizing memory arrays. The 10T SRAM-based implementation performs simple operations (like NAND, NOR, XOR) on the bitlines and other operations like addition/subtraction, shifting, rotation on custom-designed in-memory elements tightly coupled to sense amplifiers (SA). The design is verified for multiple test vectors to generate power consumption signatures. Welch’s t-test is performed on these signatures to demonstrate that the design is highly resistant to power-based SCA. The proposed implementation of ChaCha20 runs at 250MHz at a 1.2V supply, in 65nm Low Standby Power (LSTP) technology, achieving a speedup of around 7 times in terms of execution time compared to the ARM Cortex A9 processor. |
| first_indexed | 2024-12-24T01:12:40Z |
| format | Article |
| id | doaj.art-10c7122d43f642eaa7a4d1bbfcc8124d |
| institution | Directory Open Access Journal |
| issn | 2644-1225 |
| language | English |
| last_indexed | 2024-12-24T01:12:40Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj.art-10c7122d43f642eaa7a4d1bbfcc8124d2022-12-21T17:22:50ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252021-01-01283384210.1109/OJCAS.2021.31272739645047ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node DevicesM. Aamir0https://orcid.org/0000-0002-1261-1621Somya Sharma1https://orcid.org/0000-0002-8258-5262Anuj Grover2https://orcid.org/0000-0002-6057-4984Department of ECE, Indraprastha Institute of Information Technology Delhi, New Delhi, IndiaDepartment of ECE, Indraprastha Institute of Information Technology Delhi, New Delhi, IndiaDepartment of ECE, Indraprastha Institute of Information Technology Delhi, New Delhi, IndiaIoT edge devices process the data collected, which can contain sensitive information related to the user. It is crucial to incorporate robust encryption algorithms considering the resource and power budget of these devices. In this paper, we present a power-based SCA-resistant implementation of the ChaCha20 encryption algorithm for low-end devices by utilizing memory arrays. The 10T SRAM-based implementation performs simple operations (like NAND, NOR, XOR) on the bitlines and other operations like addition/subtraction, shifting, rotation on custom-designed in-memory elements tightly coupled to sense amplifiers (SA). The design is verified for multiple test vectors to generate power consumption signatures. Welch’s t-test is performed on these signatures to demonstrate that the design is highly resistant to power-based SCA. The proposed implementation of ChaCha20 runs at 250MHz at a 1.2V supply, in 65nm Low Standby Power (LSTP) technology, achieving a speedup of around 7 times in terms of execution time compared to the ARM Cortex A9 processor.https://ieeexplore.ieee.org/document/9645047/ChaCha20edge computingencryptionin-memory computeIoT securitySCA |
| spellingShingle | M. Aamir Somya Sharma Anuj Grover ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices IEEE Open Journal of Circuits and Systems ChaCha20 edge computing encryption in-memory compute IoT security SCA |
| title | ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices |
| title_full | ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices |
| title_fullStr | ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices |
| title_full_unstemmed | ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices |
| title_short | ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices |
| title_sort | chacha20 in memory for side channel resistance in iot edge node devices |
| topic | ChaCha20 edge computing encryption in-memory compute IoT security SCA |
| url | https://ieeexplore.ieee.org/document/9645047/ |
| work_keys_str_mv | AT maamir chacha20inmemoryforsidechannelresistanceiniotedgenodedevices AT somyasharma chacha20inmemoryforsidechannelresistanceiniotedgenodedevices AT anujgrover chacha20inmemoryforsidechannelresistanceiniotedgenodedevices |