IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS
The design of SRAM has evolved to suffice the need of the industry in terms of speed, power dissipation and other parameters. This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor logic to obtain better performance in terms of speed...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Taylor's University
2018-03-01
|
| Series: | Journal of Engineering Science and Technology |
| Subjects: | |
| Online Access: | http://jestec.taylors.edu.my/Vol%2013%20issue%203%20March%202018/13_3_20.pdf |
| _version_ | 1811300424779563008 |
|---|---|
| author | ROSALIND DEENA KUMARI SELVAM C. SENTHILPARI LEE LINI |
| author_facet | ROSALIND DEENA KUMARI SELVAM C. SENTHILPARI LEE LINI |
| author_sort | ROSALIND DEENA KUMARI SELVAM |
| collection | DOAJ |
| description | The design of SRAM has evolved to suffice the need of the industry in terms of speed, power dissipation and other parameters. This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor logic to obtain better performance in terms of speed, power dissipation and throughput. The dynamic logic would maintain voltage degradation by using the PMOS and NMOS transistor just as the CMOS logic, even though the design cell uses majority NMOS transistors. The proposed circuits are simulated using BSIM for different CMOS feature sizes of 70 nm, 90 nm, 120 nm and 180 nm. The results obtained have been analysed and shows that the proposed circuit of 8T performs much better as compared to other circuit configurations. There is significant improvement in power dissipation by 99.64 %, delay by 99.9 %, throughput of 490 Mbps and power delay product of 99.96 %. |
| first_indexed | 2024-04-13T06:50:56Z |
| format | Article |
| id | doaj.art-10eb410592ef4719a362d7dfe4fc39a4 |
| institution | Directory Open Access Journal |
| issn | 1823-4690 |
| language | English |
| last_indexed | 2024-04-13T06:50:56Z |
| publishDate | 2018-03-01 |
| publisher | Taylor's University |
| record_format | Article |
| series | Journal of Engineering Science and Technology |
| spelling | doaj.art-10eb410592ef4719a362d7dfe4fc39a42022-12-22T02:57:24ZengTaylor's UniversityJournal of Engineering Science and Technology1823-46902018-03-01133822837IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITSROSALIND DEENA KUMARI SELVAM0C. SENTHILPARI1LEE LINI2Faculty of Computing and Informatics, Multimedia University, Cyberjaya, 63100, Selangor DE, MalaysiaFaculty of Engineering, Multimedia University, Cyberjaya, 63100, Selangor DE, MalaysiaFaculty of Engineering, Multimedia University, Cyberjaya, 63100, Selangor DE, MalaysiaThe design of SRAM has evolved to suffice the need of the industry in terms of speed, power dissipation and other parameters. This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor logic to obtain better performance in terms of speed, power dissipation and throughput. The dynamic logic would maintain voltage degradation by using the PMOS and NMOS transistor just as the CMOS logic, even though the design cell uses majority NMOS transistors. The proposed circuits are simulated using BSIM for different CMOS feature sizes of 70 nm, 90 nm, 120 nm and 180 nm. The results obtained have been analysed and shows that the proposed circuit of 8T performs much better as compared to other circuit configurations. There is significant improvement in power dissipation by 99.64 %, delay by 99.9 %, throughput of 490 Mbps and power delay product of 99.96 %.http://jestec.taylors.edu.my/Vol%2013%20issue%203%20March%202018/13_3_20.pdfImproved speedDynamic logicSRAMLDPCThroughputPower dissipation. |
| spellingShingle | ROSALIND DEENA KUMARI SELVAM C. SENTHILPARI LEE LINI IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS Journal of Engineering Science and Technology Improved speed Dynamic logic SRAM LDPC Throughput Power dissipation. |
| title | IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS |
| title_full | IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS |
| title_fullStr | IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS |
| title_full_unstemmed | IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS |
| title_short | IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS |
| title_sort | improved speed low power and low voltage sram design for ldpc application circuits |
| topic | Improved speed Dynamic logic SRAM LDPC Throughput Power dissipation. |
| url | http://jestec.taylors.edu.my/Vol%2013%20issue%203%20March%202018/13_3_20.pdf |
| work_keys_str_mv | AT rosalinddeenakumariselvam improvedspeedlowpowerandlowvoltagesramdesignforldpcapplicationcircuits AT csenthilpari improvedspeedlowpowerandlowvoltagesramdesignforldpcapplicationcircuits AT leelini improvedspeedlowpowerandlowvoltagesramdesignforldpcapplicationcircuits |