Novel Low-Complexity and Low-Power Flip-Flop Design
In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxi...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2020-05-01
|
| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/9/5/783 |
| _version_ | 1797568377859866624 |
|---|---|
| author | Jin-Fa Lin Zheng-Jie Hong Chang-Ming Tsai Bo-Cheng Wu Shao-Wei Yu |
| author_facet | Jin-Fa Lin Zheng-Jie Hong Chang-Ming Tsai Bo-Cheng Wu Shao-Wei Yu |
| author_sort | Jin-Fa Lin |
| collection | DOAJ |
| description | In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%. |
| first_indexed | 2024-03-10T19:55:08Z |
| format | Article |
| id | doaj.art-112828526eb5491ea1193956d9395f9d |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T19:55:08Z |
| publishDate | 2020-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-112828526eb5491ea1193956d9395f9d2023-11-19T23:57:42ZengMDPI AGElectronics2079-92922020-05-019578310.3390/electronics9050783Novel Low-Complexity and Low-Power Flip-Flop DesignJin-Fa Lin0Zheng-Jie Hong1Chang-Ming Tsai2Bo-Cheng Wu3Shao-Wei Yu4Department of Information and Communication, Chaoyang University of Technology, Taichung 41349, TaiwanDepartment of Information and Communication, Chaoyang University of Technology, Taichung 41349, TaiwanDepartment of Information and Communication, Chaoyang University of Technology, Taichung 41349, TaiwanDepartment of Information and Communication, Chaoyang University of Technology, Taichung 41349, TaiwanDepartment of Information and Communication, Chaoyang University of Technology, Taichung 41349, TaiwanIn this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.https://www.mdpi.com/2079-9292/9/5/783low powerflip-floppass transistor logicInternet of Things |
| spellingShingle | Jin-Fa Lin Zheng-Jie Hong Chang-Ming Tsai Bo-Cheng Wu Shao-Wei Yu Novel Low-Complexity and Low-Power Flip-Flop Design Electronics low power flip-flop pass transistor logic Internet of Things |
| title | Novel Low-Complexity and Low-Power Flip-Flop Design |
| title_full | Novel Low-Complexity and Low-Power Flip-Flop Design |
| title_fullStr | Novel Low-Complexity and Low-Power Flip-Flop Design |
| title_full_unstemmed | Novel Low-Complexity and Low-Power Flip-Flop Design |
| title_short | Novel Low-Complexity and Low-Power Flip-Flop Design |
| title_sort | novel low complexity and low power flip flop design |
| topic | low power flip-flop pass transistor logic Internet of Things |
| url | https://www.mdpi.com/2079-9292/9/5/783 |
| work_keys_str_mv | AT jinfalin novellowcomplexityandlowpowerflipflopdesign AT zhengjiehong novellowcomplexityandlowpowerflipflopdesign AT changmingtsai novellowcomplexityandlowpowerflipflopdesign AT bochengwu novellowcomplexityandlowpowerflipflopdesign AT shaoweiyu novellowcomplexityandlowpowerflipflopdesign |