A High-Throughput Processor for GDN-Based Deep Learning Image Compression
Deep learning-based image compression techniques can take advantage of the autoencoder’s benefits to achieve greater compression quality at the same bit rate as traditional image compression, which is more in line with user desires. Designing a high-performance processor that can increase the infere...
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2023-05-01
|
| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/12/10/2289 |
| _version_ | 1797600288389988352 |
|---|---|
| author | Hu Shao Bingtao Liu Zongpeng Li Chenggang Yan Yaoqi Sun Tingyu Wang |
| author_facet | Hu Shao Bingtao Liu Zongpeng Li Chenggang Yan Yaoqi Sun Tingyu Wang |
| author_sort | Hu Shao |
| collection | DOAJ |
| description | Deep learning-based image compression techniques can take advantage of the autoencoder’s benefits to achieve greater compression quality at the same bit rate as traditional image compression, which is more in line with user desires. Designing a high-performance processor that can increase the inference speed and efficiency of the deep learning image compression (DIC) network is important to make this technology more extensively employed in mobile devices. To the best of our knowledge, there is no dedicated processor that can accelerate DIC with low power consumption, and general-purpose network accelerators based on field programmable gate arrays (FPGA) cannot directly process compressed networks, so we propose a processor suitable for DIC in this paper. First, we analyze the image compression algorithm and quantize the data of the network into 16-bit fixed points using a dynamic hierarchical quantization. Then, we design an operation module, which is the core computational part for processing. It is composed of convolution, sampling, and normalization units, which pipeline the inference calculation for each layer of the network. To achieve high-throughput inference computing, the processing elements group (PEG) array with local buffers is developed for convolutional computation. Based on the common components in encoding and decoding, the sampling and normalization units are compatible with codec computation and utilized for image compression with time-sharing multiplexing. According to the control signal, the operation module could change the order of data flow through the three units so that they perform encoding and decoding operations, respectively. Based on these design methods and schemes, DIC is deployed into the Xilinx Zynq ZCU104 development board to achieve high-throughput image compression at 6 different bit rates. The experimental results show that the processor can run at 200 MHz and achieve 283.4 GOPS for the 16 bits fixed-point DIC network. |
| first_indexed | 2024-03-11T03:46:23Z |
| format | Article |
| id | doaj.art-11395a6e4b524200910a183f5d747320 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-11T03:46:23Z |
| publishDate | 2023-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-11395a6e4b524200910a183f5d7473202023-11-18T01:10:19ZengMDPI AGElectronics2079-92922023-05-011210228910.3390/electronics12102289A High-Throughput Processor for GDN-Based Deep Learning Image CompressionHu Shao0Bingtao Liu1Zongpeng Li2Chenggang Yan3Yaoqi Sun4Tingyu Wang5Institute of Information and Control, Hangzhou Dianzi University, Hangzhou 310000, ChinaInstitute of Information and Control, Hangzhou Dianzi University, Hangzhou 310000, ChinaInstitute of Information and Control, Hangzhou Dianzi University, Hangzhou 310000, ChinaInstitute of Information and Control, Hangzhou Dianzi University, Hangzhou 310000, ChinaInstitute of Information and Control, Hangzhou Dianzi University, Hangzhou 310000, ChinaInstitute of Information and Control, Hangzhou Dianzi University, Hangzhou 310000, ChinaDeep learning-based image compression techniques can take advantage of the autoencoder’s benefits to achieve greater compression quality at the same bit rate as traditional image compression, which is more in line with user desires. Designing a high-performance processor that can increase the inference speed and efficiency of the deep learning image compression (DIC) network is important to make this technology more extensively employed in mobile devices. To the best of our knowledge, there is no dedicated processor that can accelerate DIC with low power consumption, and general-purpose network accelerators based on field programmable gate arrays (FPGA) cannot directly process compressed networks, so we propose a processor suitable for DIC in this paper. First, we analyze the image compression algorithm and quantize the data of the network into 16-bit fixed points using a dynamic hierarchical quantization. Then, we design an operation module, which is the core computational part for processing. It is composed of convolution, sampling, and normalization units, which pipeline the inference calculation for each layer of the network. To achieve high-throughput inference computing, the processing elements group (PEG) array with local buffers is developed for convolutional computation. Based on the common components in encoding and decoding, the sampling and normalization units are compatible with codec computation and utilized for image compression with time-sharing multiplexing. According to the control signal, the operation module could change the order of data flow through the three units so that they perform encoding and decoding operations, respectively. Based on these design methods and schemes, DIC is deployed into the Xilinx Zynq ZCU104 development board to achieve high-throughput image compression at 6 different bit rates. The experimental results show that the processor can run at 200 MHz and achieve 283.4 GOPS for the 16 bits fixed-point DIC network.https://www.mdpi.com/2079-9292/12/10/2289deep learning image compressionFPGA-based acceleratorgeneralized divisive normalizationhigh-throughput |
| spellingShingle | Hu Shao Bingtao Liu Zongpeng Li Chenggang Yan Yaoqi Sun Tingyu Wang A High-Throughput Processor for GDN-Based Deep Learning Image Compression Electronics deep learning image compression FPGA-based accelerator generalized divisive normalization high-throughput |
| title | A High-Throughput Processor for GDN-Based Deep Learning Image Compression |
| title_full | A High-Throughput Processor for GDN-Based Deep Learning Image Compression |
| title_fullStr | A High-Throughput Processor for GDN-Based Deep Learning Image Compression |
| title_full_unstemmed | A High-Throughput Processor for GDN-Based Deep Learning Image Compression |
| title_short | A High-Throughput Processor for GDN-Based Deep Learning Image Compression |
| title_sort | high throughput processor for gdn based deep learning image compression |
| topic | deep learning image compression FPGA-based accelerator generalized divisive normalization high-throughput |
| url | https://www.mdpi.com/2079-9292/12/10/2289 |
| work_keys_str_mv | AT hushao ahighthroughputprocessorforgdnbaseddeeplearningimagecompression AT bingtaoliu ahighthroughputprocessorforgdnbaseddeeplearningimagecompression AT zongpengli ahighthroughputprocessorforgdnbaseddeeplearningimagecompression AT chenggangyan ahighthroughputprocessorforgdnbaseddeeplearningimagecompression AT yaoqisun ahighthroughputprocessorforgdnbaseddeeplearningimagecompression AT tingyuwang ahighthroughputprocessorforgdnbaseddeeplearningimagecompression AT hushao highthroughputprocessorforgdnbaseddeeplearningimagecompression AT bingtaoliu highthroughputprocessorforgdnbaseddeeplearningimagecompression AT zongpengli highthroughputprocessorforgdnbaseddeeplearningimagecompression AT chenggangyan highthroughputprocessorforgdnbaseddeeplearningimagecompression AT yaoqisun highthroughputprocessorforgdnbaseddeeplearningimagecompression AT tingyuwang highthroughputprocessorforgdnbaseddeeplearningimagecompression |