| Summary: | Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process.
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