Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors
Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latche...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-09-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/12/19/4069 |
| _version_ | 1797575985841831936 |
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| author | Guangzhen Dai Xingyan Du Wenxin Xie Tianming Ni Mingjun Han Daohua Wu |
| author_facet | Guangzhen Dai Xingyan Du Wenxin Xie Tianming Ni Mingjun Han Daohua Wu |
| author_sort | Guangzhen Dai |
| collection | DOAJ |
| description | Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process. |
| first_indexed | 2024-03-10T21:46:20Z |
| format | Article |
| id | doaj.art-1161483c888f45e9be415a3162e0bb39 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T21:46:20Z |
| publishDate | 2023-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-1161483c888f45e9be415a3162e0bb392023-11-19T14:16:48ZengMDPI AGElectronics2079-92922023-09-011219406910.3390/electronics12194069Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on MemristorsGuangzhen Dai0Xingyan Du1Wenxin Xie2Tianming Ni3Mingjun Han4Daohua Wu5Engineering Research Center of Vehicle Display Integrated System, Anhui Polytechnic University, Wuhu 241000, ChinaSchool of Integrated Circuit, Anhui Polytechnic University, Wuhu 241000, ChinaSchool of Integrated Circuit, Anhui Polytechnic University, Wuhu 241000, ChinaEngineering Research Center of Vehicle Display Integrated System, Anhui Polytechnic University, Wuhu 241000, ChinaEngineering Research Center of Vehicle Display Integrated System, Anhui Polytechnic University, Wuhu 241000, ChinaEngineering Research Center of Vehicle Display Integrated System, Anhui Polytechnic University, Wuhu 241000, ChinaGiven its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process.https://www.mdpi.com/2079-9292/12/19/4069memristorlogic circuitD-flip-flopDFFflash ADC |
| spellingShingle | Guangzhen Dai Xingyan Du Wenxin Xie Tianming Ni Mingjun Han Daohua Wu Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors Electronics memristor logic circuit D-flip-flop DFF flash ADC |
| title | Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors |
| title_full | Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors |
| title_fullStr | Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors |
| title_full_unstemmed | Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors |
| title_short | Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors |
| title_sort | circuit design of 3 and 4 bit flash analog to digital converters based on memristors |
| topic | memristor logic circuit D-flip-flop DFF flash ADC |
| url | https://www.mdpi.com/2079-9292/12/19/4069 |
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