Circuit centric quantum architecture design
Abstract With the development in the field of quantum physics, several methods for building a quantum computer have emerged. These differ in qubit technologies, interaction topologies, and noise characteristics. In this article, insights are given into the circuit‐centric architecture design of Nois...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-03-01
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| Series: | IET Quantum Communication |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/qtc2.12004 |
| _version_ | 1811220197675106304 |
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| author | Utkarsh Azad Ankit Papneja Rakesh Saini Bikash K. Behera Prasanta K. Panigrahi |
| author_facet | Utkarsh Azad Ankit Papneja Rakesh Saini Bikash K. Behera Prasanta K. Panigrahi |
| author_sort | Utkarsh Azad |
| collection | DOAJ |
| description | Abstract With the development in the field of quantum physics, several methods for building a quantum computer have emerged. These differ in qubit technologies, interaction topologies, and noise characteristics. In this article, insights are given into the circuit‐centric architecture design of Noisy Intermediate‐Scale Quantum (NISQ) devices. The dependence of the circuit size, circuit depth on the interaction and connection between different qubits present in quantum hardware are discussed. A noise‐aware procedure is presented which helps in determining the optimal interactions between different qubits of a quantum chip to execute a given circuit in the most efficient way possible. In this article, the 5‐qubit hardware in a noiseless setting is illustrated with an example. Also, a benchmark‐driven analysis is performed to show the importance of noise adaptivity in determining the hardware reliability. It is concluded that a generalized and flexible procedure such as this approach can aid in determining the design of hardware accurately for which the circuit runs efficiently, that is, with the least number of clock cycles, the lowest gate operations, and noise‐based errors. |
| first_indexed | 2024-04-12T07:37:33Z |
| format | Article |
| id | doaj.art-11cfed6ccd0547fabb628dc5e655ef83 |
| institution | Directory Open Access Journal |
| issn | 2632-8925 |
| language | English |
| last_indexed | 2024-04-12T07:37:33Z |
| publishDate | 2021-03-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Quantum Communication |
| spelling | doaj.art-11cfed6ccd0547fabb628dc5e655ef832022-12-22T03:41:53ZengWileyIET Quantum Communication2632-89252021-03-0121142510.1049/qtc2.12004Circuit centric quantum architecture designUtkarsh Azad0Ankit Papneja1Rakesh Saini2Bikash K. Behera3Prasanta K. Panigrahi4Center for Computational Natural Sciences and Bioinformatics International Institute of Information Technology Hyderabad Telangana IndiaDepartment of Physics Indian Institute of Technology (Indian School of Mines) Dhanbad Jharkhand IndiaDepartment of Physics Indian Institute of Technology (Indian School of Mines) Dhanbad Jharkhand IndiaBikash's Quantum (OPC) Pvt. Ltd. Balindi Nadia West Bengal IndiaDepartment of Physical Sciences Indian Institute of Science Education and Research Kolkata Mohanpur West Bengal IndiaAbstract With the development in the field of quantum physics, several methods for building a quantum computer have emerged. These differ in qubit technologies, interaction topologies, and noise characteristics. In this article, insights are given into the circuit‐centric architecture design of Noisy Intermediate‐Scale Quantum (NISQ) devices. The dependence of the circuit size, circuit depth on the interaction and connection between different qubits present in quantum hardware are discussed. A noise‐aware procedure is presented which helps in determining the optimal interactions between different qubits of a quantum chip to execute a given circuit in the most efficient way possible. In this article, the 5‐qubit hardware in a noiseless setting is illustrated with an example. Also, a benchmark‐driven analysis is performed to show the importance of noise adaptivity in determining the hardware reliability. It is concluded that a generalized and flexible procedure such as this approach can aid in determining the design of hardware accurately for which the circuit runs efficiently, that is, with the least number of clock cycles, the lowest gate operations, and noise‐based errors.https://doi.org/10.1049/qtc2.12004computer architecturequantum computing |
| spellingShingle | Utkarsh Azad Ankit Papneja Rakesh Saini Bikash K. Behera Prasanta K. Panigrahi Circuit centric quantum architecture design IET Quantum Communication computer architecture quantum computing |
| title | Circuit centric quantum architecture design |
| title_full | Circuit centric quantum architecture design |
| title_fullStr | Circuit centric quantum architecture design |
| title_full_unstemmed | Circuit centric quantum architecture design |
| title_short | Circuit centric quantum architecture design |
| title_sort | circuit centric quantum architecture design |
| topic | computer architecture quantum computing |
| url | https://doi.org/10.1049/qtc2.12004 |
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