A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers
In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to th...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-02-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | https://www.mdpi.com/2079-9268/12/1/12 |
| _version_ | 1797470343897546752 |
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| author | Francesco Centurelli Riccardo Della Sala Pietro Monsurrò Giuseppe Scotti Alessandro Trifiletti |
| author_facet | Francesco Centurelli Riccardo Della Sala Pietro Monsurrò Giuseppe Scotti Alessandro Trifiletti |
| author_sort | Francesco Centurelli |
| collection | DOAJ |
| description | In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes. |
| first_indexed | 2024-03-09T19:35:14Z |
| format | Article |
| id | doaj.art-1252e89df60b40edb89602cd0f0f3f00 |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-03-09T19:35:14Z |
| publishDate | 2022-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-1252e89df60b40edb89602cd0f0f3f002023-11-24T01:55:58ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682022-02-011211210.3390/jlpea12010012A Tree-Based Architecture for High-Performance Ultra-Low-Voltage AmplifiersFrancesco Centurelli0Riccardo Della Sala1Pietro Monsurrò2Giuseppe Scotti3Alessandro Trifiletti4Dipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni (DIET), Università di Roma La Sapienza, 00184 Roma, ItalyDipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni (DIET), Università di Roma La Sapienza, 00184 Roma, ItalyDipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni (DIET), Università di Roma La Sapienza, 00184 Roma, ItalyDipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni (DIET), Università di Roma La Sapienza, 00184 Roma, ItalyDipartimento di Ingegneria dell’Informazione, Elettronica e Telecomunicazioni (DIET), Università di Roma La Sapienza, 00184 Roma, ItalyIn this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.https://www.mdpi.com/2079-9268/12/1/12body-drivenultra-low-voltageultra-low-poweroperational transconductance amplifierIoT |
| spellingShingle | Francesco Centurelli Riccardo Della Sala Pietro Monsurrò Giuseppe Scotti Alessandro Trifiletti A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers Journal of Low Power Electronics and Applications body-driven ultra-low-voltage ultra-low-power operational transconductance amplifier IoT |
| title | A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers |
| title_full | A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers |
| title_fullStr | A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers |
| title_full_unstemmed | A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers |
| title_short | A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers |
| title_sort | tree based architecture for high performance ultra low voltage amplifiers |
| topic | body-driven ultra-low-voltage ultra-low-power operational transconductance amplifier IoT |
| url | https://www.mdpi.com/2079-9268/12/1/12 |
| work_keys_str_mv | AT francescocenturelli atreebasedarchitectureforhighperformanceultralowvoltageamplifiers AT riccardodellasala atreebasedarchitectureforhighperformanceultralowvoltageamplifiers AT pietromonsurro atreebasedarchitectureforhighperformanceultralowvoltageamplifiers AT giuseppescotti atreebasedarchitectureforhighperformanceultralowvoltageamplifiers AT alessandrotrifiletti atreebasedarchitectureforhighperformanceultralowvoltageamplifiers AT francescocenturelli treebasedarchitectureforhighperformanceultralowvoltageamplifiers AT riccardodellasala treebasedarchitectureforhighperformanceultralowvoltageamplifiers AT pietromonsurro treebasedarchitectureforhighperformanceultralowvoltageamplifiers AT giuseppescotti treebasedarchitectureforhighperformanceultralowvoltageamplifiers AT alessandrotrifiletti treebasedarchitectureforhighperformanceultralowvoltageamplifiers |