Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations
Several different designs of 1.2kV-rated 4H-SiC MOSFETs have been successfully fabricated under various ion implantation conditions. Implantation conditions consisted of different P+ profiles and implantation temperatures of both room temperature (25°C) and elevated temperature...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10416803/ |
| _version_ | 1826852319333974016 |
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| author | Stephen A. Mancini Seung Yup Jang Zeyu Chen Dongyoung Kim Alex Bialy Balaji Raghotamacher Michael Dudley Nadeemullah Mahadik Robert Stahlbush Mowafak Al-Jassim Woongje Sung |
| author_facet | Stephen A. Mancini Seung Yup Jang Zeyu Chen Dongyoung Kim Alex Bialy Balaji Raghotamacher Michael Dudley Nadeemullah Mahadik Robert Stahlbush Mowafak Al-Jassim Woongje Sung |
| author_sort | Stephen A. Mancini |
| collection | DOAJ |
| description | Several different designs of 1.2kV-rated 4H-SiC MOSFETs have been successfully fabricated under various ion implantation conditions. Implantation conditions consisted of different P+ profiles and implantation temperatures of both room temperature (25°C) and elevated temperatures (600°C) in order to monitor subsequent lattice damage. Through the use of X-Ray topography, SEM imaging, and electrical measurements, it was shown that room temperature implanted devices can mimic the static performances of high temperature implanted MOSFETs and reduce lattice damage suffered during the fabrication process, when the dose of high energy implants are suppressed. |
| first_indexed | 2024-03-07T19:11:57Z |
| format | Article |
| id | doaj.art-1270876fa2c248cda42a97598fc69977 |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2025-02-16T17:04:40Z |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-1270876fa2c248cda42a97598fc699772025-01-29T00:00:11ZengIEEEIEEE Journal of the Electron Devices Society2168-67342024-01-011215015810.1109/JEDS.2024.335997410416803Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion ImplantationsStephen A. Mancini0https://orcid.org/0009-0007-9126-8721Seung Yup Jang1https://orcid.org/0000-0002-2202-8800Zeyu Chen2Dongyoung Kim3Alex Bialy4Balaji Raghotamacher5https://orcid.org/0000-0003-4684-2716Michael Dudley6Nadeemullah Mahadik7Robert Stahlbush8Mowafak Al-Jassim9Woongje Sung10https://orcid.org/0000-0003-0960-5973College of Nanotechnology Science and Engineering, University at Albany, Albany, NY, USACollege of Nanotechnology Science and Engineering, University at Albany, Albany, NY, USADepartment of Material Science and Chemical Engineering, Stony Brook University, Stony Brook, NY, USACollege of Nanotechnology Science and Engineering, University at Albany, Albany, NY, USACollege of Nanotechnology Science and Engineering, University at Albany, Albany, NY, USADepartment of Material Science and Chemical Engineering, Stony Brook University, Stony Brook, NY, USADepartment of Material Science and Chemical Engineering, Stony Brook University, Stony Brook, NY, USANaval Research Laboratory, Washington, DC, USANaval Research Laboratory, Washington, DC, USANational Renewable Energy Laboratory, Golden, CO, USACollege of Nanotechnology Science and Engineering, University at Albany, Albany, NY, USASeveral different designs of 1.2kV-rated 4H-SiC MOSFETs have been successfully fabricated under various ion implantation conditions. Implantation conditions consisted of different P+ profiles and implantation temperatures of both room temperature (25°C) and elevated temperatures (600°C) in order to monitor subsequent lattice damage. Through the use of X-Ray topography, SEM imaging, and electrical measurements, it was shown that room temperature implanted devices can mimic the static performances of high temperature implanted MOSFETs and reduce lattice damage suffered during the fabrication process, when the dose of high energy implants are suppressed.https://ieeexplore.ieee.org/document/10416803/4H-Silicon Carbide (SiC)MOSFET3rd quadrantdesign approachleakage currentbreakdown voltage |
| spellingShingle | Stephen A. Mancini Seung Yup Jang Zeyu Chen Dongyoung Kim Alex Bialy Balaji Raghotamacher Michael Dudley Nadeemullah Mahadik Robert Stahlbush Mowafak Al-Jassim Woongje Sung Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations IEEE Journal of the Electron Devices Society 4H-Silicon Carbide (SiC) MOSFET 3rd quadrant design approach leakage current breakdown voltage |
| title | Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations |
| title_full | Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations |
| title_fullStr | Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations |
| title_full_unstemmed | Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations |
| title_short | Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations |
| title_sort | investigation of static performances of 1 2kv 4h sic mosfets fabricated using all x2018 room temperature x2019 ion implantations |
| topic | 4H-Silicon Carbide (SiC) MOSFET 3rd quadrant design approach leakage current breakdown voltage |
| url | https://ieeexplore.ieee.org/document/10416803/ |
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