Energy-Efficient Variation-Resilient High-Throughput Processor Design
Background and Objectives: The future demands of multimedia and signal processing applications forced the IC designers to utilize efficient high performance techniques in more complex SoCs to achieve higher computing throughput besides energy/power efficiency improvement. In recent technologies, var...
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| Format: | Article |
| Language: | English |
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Shahid Rajaee Teacher Training University
2022-07-01
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| Series: | Journal of Electrical and Computer Engineering Innovations |
| Subjects: | |
| Online Access: | https://jecei.sru.ac.ir/article_1637_92851aee0786ca7b1164228d0cb741bd.pdf |
| _version_ | 1811334670151843840 |
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| author | A. Teymouri H. Dorosti M. Ersali Salehi Nasab S.M. Fakhraie |
| author_facet | A. Teymouri H. Dorosti M. Ersali Salehi Nasab S.M. Fakhraie |
| author_sort | A. Teymouri |
| collection | DOAJ |
| description | Background and Objectives: The future demands of multimedia and signal processing applications forced the IC designers to utilize efficient high performance techniques in more complex SoCs to achieve higher computing throughput besides energy/power efficiency improvement. In recent technologies, variation effects and leakage power highly affect the design specifications and designers need to consider these parameters in design time. Considering both challenges as well as boosting the computation throughput makes the design more difficult.Methods: In this article, we propose a simple serial core for higher energy/power efficiency and also utilize data level parallel structures to achieve required computation throughput.Results: Using the proposed core we have 35% (75%) energy (power) improvement and also using parallel structure results in 8x higher throughput. The proposed architecture is able to provide 76 MIPS computation throughput by consuming only 2.7 pj per instruction. The outstanding feature of this processor is its resiliency against the variation effects.Conclusion: Simple serial architecture reduces the effect of variations on design paths, furthermore, the effect of process variation on throughput loss and energy dissipation is negligible and almost zero. Proposed processor architecture is proper for energy/power constrained applications such as internet of things (IoT) and mobile devices to enable easy energy harvesting for longer lifetime. |
| first_indexed | 2024-04-13T17:11:32Z |
| format | Article |
| id | doaj.art-131dbd3dc6d04e749391dbd165b07f17 |
| institution | Directory Open Access Journal |
| issn | 2322-3952 2345-3044 |
| language | English |
| last_indexed | 2024-04-13T17:11:32Z |
| publishDate | 2022-07-01 |
| publisher | Shahid Rajaee Teacher Training University |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering Innovations |
| spelling | doaj.art-131dbd3dc6d04e749391dbd165b07f172022-12-22T02:38:15ZengShahid Rajaee Teacher Training UniversityJournal of Electrical and Computer Engineering Innovations2322-39522345-30442022-07-0110229931010.22061/jecei.2021.8253.4991637Energy-Efficient Variation-Resilient High-Throughput Processor DesignA. Teymouri0H. Dorosti1M. Ersali Salehi Nasab2S.M. Fakhraie3Nano-Electronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran.Department of Computer Systems Architecture, Faculty of Computer Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran.Nano-Electronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran.Nano-Electronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran.Background and Objectives: The future demands of multimedia and signal processing applications forced the IC designers to utilize efficient high performance techniques in more complex SoCs to achieve higher computing throughput besides energy/power efficiency improvement. In recent technologies, variation effects and leakage power highly affect the design specifications and designers need to consider these parameters in design time. Considering both challenges as well as boosting the computation throughput makes the design more difficult.Methods: In this article, we propose a simple serial core for higher energy/power efficiency and also utilize data level parallel structures to achieve required computation throughput.Results: Using the proposed core we have 35% (75%) energy (power) improvement and also using parallel structure results in 8x higher throughput. The proposed architecture is able to provide 76 MIPS computation throughput by consuming only 2.7 pj per instruction. The outstanding feature of this processor is its resiliency against the variation effects.Conclusion: Simple serial architecture reduces the effect of variations on design paths, furthermore, the effect of process variation on throughput loss and energy dissipation is negligible and almost zero. Proposed processor architecture is proper for energy/power constrained applications such as internet of things (IoT) and mobile devices to enable easy energy harvesting for longer lifetime.https://jecei.sru.ac.ir/article_1637_92851aee0786ca7b1164228d0cb741bd.pdfmassive parallel processingsstaultra-low-energyvariation-awarehigh-throughput |
| spellingShingle | A. Teymouri H. Dorosti M. Ersali Salehi Nasab S.M. Fakhraie Energy-Efficient Variation-Resilient High-Throughput Processor Design Journal of Electrical and Computer Engineering Innovations massive parallel processing ssta ultra-low-energy variation-aware high-throughput |
| title | Energy-Efficient Variation-Resilient High-Throughput Processor Design |
| title_full | Energy-Efficient Variation-Resilient High-Throughput Processor Design |
| title_fullStr | Energy-Efficient Variation-Resilient High-Throughput Processor Design |
| title_full_unstemmed | Energy-Efficient Variation-Resilient High-Throughput Processor Design |
| title_short | Energy-Efficient Variation-Resilient High-Throughput Processor Design |
| title_sort | energy efficient variation resilient high throughput processor design |
| topic | massive parallel processing ssta ultra-low-energy variation-aware high-throughput |
| url | https://jecei.sru.ac.ir/article_1637_92851aee0786ca7b1164228d0cb741bd.pdf |
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