Efficient Convolutional Neural Networks for Semiconductor Wafer Bin Map Classification
The results obtained in the wafer test process are expressed as a wafer map and contain important information indicating whether each chip on the wafer is functioning normally. The defect patterns shown on the wafer map provide information about the process and equipment in which the defect occurred...
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| Format: | Article |
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MDPI AG
2023-02-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/23/4/1926 |
| _version_ | 1797618254387085312 |
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| author | Eunmi Shin Chang D. Yoo |
| author_facet | Eunmi Shin Chang D. Yoo |
| author_sort | Eunmi Shin |
| collection | DOAJ |
| description | The results obtained in the wafer test process are expressed as a wafer map and contain important information indicating whether each chip on the wafer is functioning normally. The defect patterns shown on the wafer map provide information about the process and equipment in which the defect occurred, but automating pattern classification is difficult to apply to actual manufacturing sites unless processing speed and resource efficiency are supported. The purpose of this study was to classify these defect patterns with a small amount of resources and time. To this end, we explored an efficient convolutional neural network model that can incorporate three properties: (1) state-of-the-art performances, (2) less resource usage, and (3) faster processing time. In this study, we dealt with classifying nine types of frequently found defect patterns: center, donut, edge-location, edge-ring, location, random, scratch, near-full type, and None type using open dataset WM-811K. We compared classification performance, resource usage, and processing time using EfficientNetV2, ShuffleNetV2, MobileNetV2 and MobileNetV3, which are the smallest and latest light-weight convolutional neural network models. As a result, the MobileNetV3-based wafer map pattern classifier uses 7.5 times fewer parameters than ResNet, and the training speed is 7.2 times and the inference speed is 4.9 times faster, while the accuracy is 98% and the F1 score is 89.5%, achieving the same level. Therefore, it can be proved that it can be used as a wafer map classification model without high-performance hardware in an actual manufacturing system. |
| first_indexed | 2024-03-11T08:10:30Z |
| format | Article |
| id | doaj.art-1476dd464b85471abcb658c90410cde9 |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-11T08:10:30Z |
| publishDate | 2023-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-1476dd464b85471abcb658c90410cde92023-11-16T23:07:59ZengMDPI AGSensors1424-82202023-02-01234192610.3390/s23041926Efficient Convolutional Neural Networks for Semiconductor Wafer Bin Map ClassificationEunmi Shin0Chang D. Yoo1Korea Advanced Institute of Science and Technology, Daejeon 34141, Republic of KoreaKorea Advanced Institute of Science and Technology, Daejeon 34141, Republic of KoreaThe results obtained in the wafer test process are expressed as a wafer map and contain important information indicating whether each chip on the wafer is functioning normally. The defect patterns shown on the wafer map provide information about the process and equipment in which the defect occurred, but automating pattern classification is difficult to apply to actual manufacturing sites unless processing speed and resource efficiency are supported. The purpose of this study was to classify these defect patterns with a small amount of resources and time. To this end, we explored an efficient convolutional neural network model that can incorporate three properties: (1) state-of-the-art performances, (2) less resource usage, and (3) faster processing time. In this study, we dealt with classifying nine types of frequently found defect patterns: center, donut, edge-location, edge-ring, location, random, scratch, near-full type, and None type using open dataset WM-811K. We compared classification performance, resource usage, and processing time using EfficientNetV2, ShuffleNetV2, MobileNetV2 and MobileNetV3, which are the smallest and latest light-weight convolutional neural network models. As a result, the MobileNetV3-based wafer map pattern classifier uses 7.5 times fewer parameters than ResNet, and the training speed is 7.2 times and the inference speed is 4.9 times faster, while the accuracy is 98% and the F1 score is 89.5%, achieving the same level. Therefore, it can be proved that it can be used as a wafer map classification model without high-performance hardware in an actual manufacturing system.https://www.mdpi.com/1424-8220/23/4/1926wafer mapdefect patternpattern classificationlight-weight convolutional neural networks |
| spellingShingle | Eunmi Shin Chang D. Yoo Efficient Convolutional Neural Networks for Semiconductor Wafer Bin Map Classification Sensors wafer map defect pattern pattern classification light-weight convolutional neural networks |
| title | Efficient Convolutional Neural Networks for Semiconductor Wafer Bin Map Classification |
| title_full | Efficient Convolutional Neural Networks for Semiconductor Wafer Bin Map Classification |
| title_fullStr | Efficient Convolutional Neural Networks for Semiconductor Wafer Bin Map Classification |
| title_full_unstemmed | Efficient Convolutional Neural Networks for Semiconductor Wafer Bin Map Classification |
| title_short | Efficient Convolutional Neural Networks for Semiconductor Wafer Bin Map Classification |
| title_sort | efficient convolutional neural networks for semiconductor wafer bin map classification |
| topic | wafer map defect pattern pattern classification light-weight convolutional neural networks |
| url | https://www.mdpi.com/1424-8220/23/4/1926 |
| work_keys_str_mv | AT eunmishin efficientconvolutionalneuralnetworksforsemiconductorwaferbinmapclassification AT changdyoo efficientconvolutionalneuralnetworksforsemiconductorwaferbinmapclassification |