Energy-efficient algebra kernels in FPGA for High Performance Computing
The dissemination of multi-core architectures and the later irruption of massively parallel devices, led to a revolution in High-Performance Computing (HPC) platforms in the last decades. As a result, Field-Programmable Gate Arrays (FPGAs) are re-emerging as a versatile and more energy-efficient alt...
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| Format: | Article |
| Language: | English |
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Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata
2021-10-01
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| Series: | Journal of Computer Science and Technology |
| Subjects: | |
| Online Access: | https://journal.info.unlp.edu.ar/JCST/article/view/1822 |
| _version_ | 1818348555331436544 |
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| author | Federico Favaro Ernesto Dufrechou Pablo Ezzatti Juan Pablo Oliver |
| author_facet | Federico Favaro Ernesto Dufrechou Pablo Ezzatti Juan Pablo Oliver |
| author_sort | Federico Favaro |
| collection | DOAJ |
| description | The dissemination of multi-core architectures and the later irruption of massively parallel devices, led to a revolution in High-Performance Computing (HPC) platforms in the last decades. As a result, Field-Programmable Gate Arrays (FPGAs) are re-emerging as a versatile and more energy-efficient alternative to other platforms. Traditional FPGA design implies using low-level Hardware Description Languages (HDL) such as VHDL or Verilog, which follow an entirely different programming model than standard software languages, and their use requires specialized knowledge of the underlying hardware. In the last years, manufacturers started to make big efforts to provide High-Level Synthesis (HLS) tools, in order to allow a grater adoption of FPGAs in the HPC community.
Our work studies the use of multi-core hardware and different FPGAs to address Numerical Linear Algebra (NLA) kernels such as the general matrix multiplication GEMM and the sparse matrix-vector multiplication SpMV. Specifically, we compare the behavior of fine-tuned kernels in a multi-core CPU processor and HLS implementations on FPGAs. We perform the experimental evaluation of our implementations on a low-end and a cutting-edge FPGA platform, in terms of runtime and energy consumption, and compare the results against the Intel MKL library in CPU. |
| first_indexed | 2024-12-13T17:51:55Z |
| format | Article |
| id | doaj.art-159301d2831a42a0b90d6847d35a3dce |
| institution | Directory Open Access Journal |
| issn | 1666-6046 1666-6038 |
| language | English |
| last_indexed | 2024-12-13T17:51:55Z |
| publishDate | 2021-10-01 |
| publisher | Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata |
| record_format | Article |
| series | Journal of Computer Science and Technology |
| spelling | doaj.art-159301d2831a42a0b90d6847d35a3dce2022-12-21T23:36:29ZengPostgraduate Office, School of Computer Science, Universidad Nacional de La PlataJournal of Computer Science and Technology1666-60461666-60382021-10-01212e09e0910.24215/16666038.21.e092401Energy-efficient algebra kernels in FPGA for High Performance ComputingFederico Favaro0Ernesto Dufrechou1Pablo Ezzatti2Juan Pablo OliverUniversidad de la RepublicaUniversidad de la RepúblicaUniversidad de la RepúblicaThe dissemination of multi-core architectures and the later irruption of massively parallel devices, led to a revolution in High-Performance Computing (HPC) platforms in the last decades. As a result, Field-Programmable Gate Arrays (FPGAs) are re-emerging as a versatile and more energy-efficient alternative to other platforms. Traditional FPGA design implies using low-level Hardware Description Languages (HDL) such as VHDL or Verilog, which follow an entirely different programming model than standard software languages, and their use requires specialized knowledge of the underlying hardware. In the last years, manufacturers started to make big efforts to provide High-Level Synthesis (HLS) tools, in order to allow a grater adoption of FPGAs in the HPC community. Our work studies the use of multi-core hardware and different FPGAs to address Numerical Linear Algebra (NLA) kernels such as the general matrix multiplication GEMM and the sparse matrix-vector multiplication SpMV. Specifically, we compare the behavior of fine-tuned kernels in a multi-core CPU processor and HLS implementations on FPGAs. We perform the experimental evaluation of our implementations on a low-end and a cutting-edge FPGA platform, in terms of runtime and energy consumption, and compare the results against the Intel MKL library in CPU.https://journal.info.unlp.edu.ar/JCST/article/view/1822dense and sparse nlafpgahlsenergy consumption |
| spellingShingle | Federico Favaro Ernesto Dufrechou Pablo Ezzatti Juan Pablo Oliver Energy-efficient algebra kernels in FPGA for High Performance Computing Journal of Computer Science and Technology dense and sparse nla fpga hls energy consumption |
| title | Energy-efficient algebra kernels in FPGA for High Performance Computing |
| title_full | Energy-efficient algebra kernels in FPGA for High Performance Computing |
| title_fullStr | Energy-efficient algebra kernels in FPGA for High Performance Computing |
| title_full_unstemmed | Energy-efficient algebra kernels in FPGA for High Performance Computing |
| title_short | Energy-efficient algebra kernels in FPGA for High Performance Computing |
| title_sort | energy efficient algebra kernels in fpga for high performance computing |
| topic | dense and sparse nla fpga hls energy consumption |
| url | https://journal.info.unlp.edu.ar/JCST/article/view/1822 |
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