An Optimized Implementation of Activation Instruction Based on RISC-V
Activation is an important component of the neural network, and the standard instructions of RISC-V are difficult to use to effectively handle the activation of the array. In this paper, we propose an optimized implementation of activation instruction based on RISC-V. Based on the opensource RISC-V...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-04-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/12/9/1986 |
| _version_ | 1797602736780345344 |
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| author | Hongjiang Yu Guoshun Yuan Dewei Kong Chuhuai Chen |
| author_facet | Hongjiang Yu Guoshun Yuan Dewei Kong Chuhuai Chen |
| author_sort | Hongjiang Yu |
| collection | DOAJ |
| description | Activation is an important component of the neural network, and the standard instructions of RISC-V are difficult to use to effectively handle the activation of the array. In this paper, we propose an optimized implementation of activation instruction based on RISC-V. Based on the opensource RISC-V processor Hummingbird E203, we designed a special instruction for the implementation of activation functions. A single instruction is chosen to implement the entire activation operation, including data loading, data arithmetic and data write-back. At the hardware level, we designed a method of alternate reading and writing that only needs a small hardware storage unit to meet the requirements of the activation operation for long arrays without affecting the activation efficiency. In addition, we added the length of the array as a new parameter to instruct our designed hardware to adapt to any length of arrays. Finally, the scheduling method of some instructions in the activation process was optimized in accordance with the law of instructions, which improves the execution efficiency of instructions. Considering an activation process with an array length of 15, our design demonstrates a 4.89-fold increase in speed compared to RISC-V standard instructions while consuming only 7.78% of the energy. |
| first_indexed | 2024-03-11T04:20:51Z |
| format | Article |
| id | doaj.art-15a92d233a6e455ead64da64b9010889 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-11T04:20:51Z |
| publishDate | 2023-04-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-15a92d233a6e455ead64da64b90108892023-11-17T22:47:10ZengMDPI AGElectronics2079-92922023-04-01129198610.3390/electronics12091986An Optimized Implementation of Activation Instruction Based on RISC-VHongjiang Yu0Guoshun Yuan1Dewei Kong2Chuhuai Chen3Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, ChinaActivation is an important component of the neural network, and the standard instructions of RISC-V are difficult to use to effectively handle the activation of the array. In this paper, we propose an optimized implementation of activation instruction based on RISC-V. Based on the opensource RISC-V processor Hummingbird E203, we designed a special instruction for the implementation of activation functions. A single instruction is chosen to implement the entire activation operation, including data loading, data arithmetic and data write-back. At the hardware level, we designed a method of alternate reading and writing that only needs a small hardware storage unit to meet the requirements of the activation operation for long arrays without affecting the activation efficiency. In addition, we added the length of the array as a new parameter to instruct our designed hardware to adapt to any length of arrays. Finally, the scheduling method of some instructions in the activation process was optimized in accordance with the law of instructions, which improves the execution efficiency of instructions. Considering an activation process with an array length of 15, our design demonstrates a 4.89-fold increase in speed compared to RISC-V standard instructions while consuming only 7.78% of the energy.https://www.mdpi.com/2079-9292/12/9/1986activationspecial instructionsingle instruction operationalternate reading and writinglength adaptationinstruction scheduling |
| spellingShingle | Hongjiang Yu Guoshun Yuan Dewei Kong Chuhuai Chen An Optimized Implementation of Activation Instruction Based on RISC-V Electronics activation special instruction single instruction operation alternate reading and writing length adaptation instruction scheduling |
| title | An Optimized Implementation of Activation Instruction Based on RISC-V |
| title_full | An Optimized Implementation of Activation Instruction Based on RISC-V |
| title_fullStr | An Optimized Implementation of Activation Instruction Based on RISC-V |
| title_full_unstemmed | An Optimized Implementation of Activation Instruction Based on RISC-V |
| title_short | An Optimized Implementation of Activation Instruction Based on RISC-V |
| title_sort | optimized implementation of activation instruction based on risc v |
| topic | activation special instruction single instruction operation alternate reading and writing length adaptation instruction scheduling |
| url | https://www.mdpi.com/2079-9292/12/9/1986 |
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