An Improved Strong Arm Comparator With Integrated Static Preamplifier
This paper presents a novel Strong Arm comparator in which the input pair is reused as a static amplifier to preamplify the input signal during the precharge phase. The proposed approach relaxes the main trade-offs that characterize the Strong Arm latch: compared to the conventional topology, the en...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10229118/ |
| _version_ | 1797692100925456384 |
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| author | Valerio Spinogatti Riccardo Della Sala Cristian Bocciarelli Francesco Centurelli Alessandro Trifiletti |
| author_facet | Valerio Spinogatti Riccardo Della Sala Cristian Bocciarelli Francesco Centurelli Alessandro Trifiletti |
| author_sort | Valerio Spinogatti |
| collection | DOAJ |
| description | This paper presents a novel Strong Arm comparator in which the input pair is reused as a static amplifier to preamplify the input signal during the precharge phase. The proposed approach relaxes the main trade-offs that characterize the Strong Arm latch: compared to the conventional topology, the enhanced comparator achieves better input-referred noise and offset, without penalizing delay nor power consumption. In fact, the proposed topology is even more efficient than its conventional counterpart as it exhibits lower power consumption when the two circuits are sized to have the same delay. The operation of the new topology is analyzed in detail through a comprehensive theoretical analysis, providing useful design criteria. The enhanced Strong Arm comparator is validated by means of post-layout simulations in a 55 nm CMOS technology with 1 V supply. The simulations show that the proposed approach improves noise, offset and energy-delay product (EDP) respectively by 28.5%, 33.8% and 5.24% compared to the conventional Strong Arm latch. |
| first_indexed | 2024-03-12T02:23:47Z |
| format | Article |
| id | doaj.art-16713087ca254659b4470d4afd431825 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-12T02:23:47Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-16713087ca254659b4470d4afd4318252023-09-05T23:01:20ZengIEEEIEEE Access2169-35362023-01-0111917249173710.1109/ACCESS.2023.330844710229118An Improved Strong Arm Comparator With Integrated Static PreamplifierValerio Spinogatti0Riccardo Della Sala1https://orcid.org/0000-0001-9990-4875Cristian Bocciarelli2Francesco Centurelli3https://orcid.org/0000-0003-3880-2546Alessandro Trifiletti4https://orcid.org/0000-0001-6231-4273Department of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, Rome, ItalyDepartment of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, Rome, ItalyDepartment of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, Rome, ItalyDepartment of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, Rome, ItalyDepartment of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, Rome, ItalyThis paper presents a novel Strong Arm comparator in which the input pair is reused as a static amplifier to preamplify the input signal during the precharge phase. The proposed approach relaxes the main trade-offs that characterize the Strong Arm latch: compared to the conventional topology, the enhanced comparator achieves better input-referred noise and offset, without penalizing delay nor power consumption. In fact, the proposed topology is even more efficient than its conventional counterpart as it exhibits lower power consumption when the two circuits are sized to have the same delay. The operation of the new topology is analyzed in detail through a comprehensive theoretical analysis, providing useful design criteria. The enhanced Strong Arm comparator is validated by means of post-layout simulations in a 55 nm CMOS technology with 1 V supply. The simulations show that the proposed approach improves noise, offset and energy-delay product (EDP) respectively by 28.5%, 33.8% and 5.24% compared to the conventional Strong Arm latch.https://ieeexplore.ieee.org/document/10229118/Strong Armhigh speeddynamic comparatoranalog-to-digital conversion (ADC) |
| spellingShingle | Valerio Spinogatti Riccardo Della Sala Cristian Bocciarelli Francesco Centurelli Alessandro Trifiletti An Improved Strong Arm Comparator With Integrated Static Preamplifier IEEE Access Strong Arm high speed dynamic comparator analog-to-digital conversion (ADC) |
| title | An Improved Strong Arm Comparator With Integrated Static Preamplifier |
| title_full | An Improved Strong Arm Comparator With Integrated Static Preamplifier |
| title_fullStr | An Improved Strong Arm Comparator With Integrated Static Preamplifier |
| title_full_unstemmed | An Improved Strong Arm Comparator With Integrated Static Preamplifier |
| title_short | An Improved Strong Arm Comparator With Integrated Static Preamplifier |
| title_sort | improved strong arm comparator with integrated static preamplifier |
| topic | Strong Arm high speed dynamic comparator analog-to-digital conversion (ADC) |
| url | https://ieeexplore.ieee.org/document/10229118/ |
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