Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs
Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be...
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| Format: | Article |
| Language: | English |
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MDPI AG
2018-11-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/7/11/322 |
| _version_ | 1798038824315518976 |
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| author | Luis Alberto Aranda Pedro Reviriego Juan Antonio Maestro |
| author_facet | Luis Alberto Aranda Pedro Reviriego Juan Antonio Maestro |
| author_sort | Luis Alberto Aranda |
| collection | DOAJ |
| description | Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be vulnerable to configuration memory errors caused by single event upsets (SEUs). In those systems, the captured image is streamed pixel by pixel from the camera to the FPGA. Certain local operations such as median or rank filters need to process the image locally instead of pixel by pixel, so some particular pixel caching structures such as line-buffer-based pipelines can be used to accelerate the filtering process. However, an SRAM-based FPGA implementation of these pipelines may have malfunctions due to the mentioned configuration memory errors, so an error mitigation technique is required. In this paper, a novel method to protect line-buffer-based pipelines against SRAM-based FPGA configuration memory errors is presented. Experimental results show that, using our protection technique, considerable savings in terms of FPGA resources can be achieved while maintaining the SEU protection coverage provided by other classic pipeline protection schemes. |
| first_indexed | 2024-04-11T21:45:38Z |
| format | Article |
| id | doaj.art-17982d7754fd43c281283784a302846c |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-04-11T21:45:38Z |
| publishDate | 2018-11-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-17982d7754fd43c281283784a302846c2022-12-22T04:01:25ZengMDPI AGElectronics2079-92922018-11-0171132210.3390/electronics7110322electronics7110322Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAsLuis Alberto Aranda0Pedro Reviriego1Juan Antonio Maestro2ARIES Research Center, Universidad Antonio de Nebrija, Madrid 28040, SpainDepartamento de Ingeniería Telemática, Universidad Carlos III de Madrid, Leganés 28911, SpainARIES Research Center, Universidad Antonio de Nebrija, Madrid 28040, SpainImage processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be vulnerable to configuration memory errors caused by single event upsets (SEUs). In those systems, the captured image is streamed pixel by pixel from the camera to the FPGA. Certain local operations such as median or rank filters need to process the image locally instead of pixel by pixel, so some particular pixel caching structures such as line-buffer-based pipelines can be used to accelerate the filtering process. However, an SRAM-based FPGA implementation of these pipelines may have malfunctions due to the mentioned configuration memory errors, so an error mitigation technique is required. In this paper, a novel method to protect line-buffer-based pipelines against SRAM-based FPGA configuration memory errors is presented. Experimental results show that, using our protection technique, considerable savings in terms of FPGA resources can be achieved while maintaining the SEU protection coverage provided by other classic pipeline protection schemes.https://www.mdpi.com/2079-9292/7/11/322Image processingline bufferSRAM-based FPGAsingle event upset (SEU)configuration memorysoft error |
| spellingShingle | Luis Alberto Aranda Pedro Reviriego Juan Antonio Maestro Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs Electronics Image processing line buffer SRAM-based FPGA single event upset (SEU) configuration memory soft error |
| title | Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs |
| title_full | Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs |
| title_fullStr | Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs |
| title_full_unstemmed | Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs |
| title_short | Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs |
| title_sort | protecting image processing pipelines against configuration memory errors in sram based fpgas |
| topic | Image processing line buffer SRAM-based FPGA single event upset (SEU) configuration memory soft error |
| url | https://www.mdpi.com/2079-9292/7/11/322 |
| work_keys_str_mv | AT luisalbertoaranda protectingimageprocessingpipelinesagainstconfigurationmemoryerrorsinsrambasedfpgas AT pedroreviriego protectingimageprocessingpipelinesagainstconfigurationmemoryerrorsinsrambasedfpgas AT juanantoniomaestro protectingimageprocessingpipelinesagainstconfigurationmemoryerrorsinsrambasedfpgas |