The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors
Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2017-02-01
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| Series: | Sensors |
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| Online Access: | http://www.mdpi.com/1424-8220/17/2/426 |
| _version_ | 1798043260948578304 |
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| author | Seung-Ho Ok Yong-Hwan Lee Jae Hoon Shim Sung Kyu Lim Byungin Moon |
| author_facet | Seung-Ho Ok Yong-Hwan Lee Jae Hoon Shim Sung Kyu Lim Byungin Moon |
| author_sort | Seung-Ho Ok |
| collection | DOAJ |
| description | Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs. |
| first_indexed | 2024-04-11T22:46:54Z |
| format | Article |
| id | doaj.art-17ac8579196f444d92103dbf3f8d4851 |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-04-11T22:46:54Z |
| publishDate | 2017-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-17ac8579196f444d92103dbf3f8d48512022-12-22T03:58:43ZengMDPI AGSensors1424-82202017-02-0117242610.3390/s17020426s17020426The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching ProcessorsSeung-Ho Ok0Yong-Hwan Lee1Jae Hoon Shim2Sung Kyu Lim3Byungin Moon4Samsung Electronics, Hwaseong-si, Gyeonggi-do 18448, KoreaSchool of Electronic Engineering, Kumoh National Institute of Technology, Gumi 39177, KoreaSchool of Electronics Engineering, Kyungpook National University, Daegu 41566, KoreaSchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USASchool of Electronics Engineering, Kyungpook National University, Daegu 41566, KoreaRecently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.http://www.mdpi.com/1424-8220/17/2/426through-silicon viastereo matching processortechnology scalinglow-power |
| spellingShingle | Seung-Ho Ok Yong-Hwan Lee Jae Hoon Shim Sung Kyu Lim Byungin Moon The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors Sensors through-silicon via stereo matching processor technology scaling low-power |
| title | The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors |
| title_full | The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors |
| title_fullStr | The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors |
| title_full_unstemmed | The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors |
| title_short | The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors |
| title_sort | impact of 3d stacking and technology scaling on the power and area of stereo matching processors |
| topic | through-silicon via stereo matching processor technology scaling low-power |
| url | http://www.mdpi.com/1424-8220/17/2/426 |
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