A Survey on RISC-V-Based Machine Learning Ecosystem

In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and applications that have already reached a substant...

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Main Authors: Stavros Kalapothas, Manolis Galetakis, Georgios Flamis, Fotis Plessas, Paris Kitsos
Format: Article
Language:English
Published: MDPI AG 2023-01-01
Series:Information
Subjects:
Online Access:https://www.mdpi.com/2078-2489/14/2/64
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author Stavros Kalapothas
Manolis Galetakis
Georgios Flamis
Fotis Plessas
Paris Kitsos
author_facet Stavros Kalapothas
Manolis Galetakis
Georgios Flamis
Fotis Plessas
Paris Kitsos
author_sort Stavros Kalapothas
collection DOAJ
description In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and applications that have already reached a substantial growth, such as in natural language processing (NLP) and computer vision (CV). The developments of open-source hardware (OSH) and the contribution towards the creation of hardware-based accelerators with implication mainly in machine learning (ML), has also been significant. In particular, the reduced instruction-set computer-five (RISC-V) open standard architecture has been widely adopted by a community of researchers and commercial users, worldwide, in numerous openly available implementations. The selection through a plethora of RISC-V processor cores and the mix of architectures and configurations combined with the proliferation of ML software frameworks for ML workloads, is not trivial. In order to facilitate this process, this paper presents a survey focused on the assessment of the ecosystem that entails RISC-V based hardware for creating a classification of system-on-chip (SoC) and CPU cores, along with an inclusive arrangement of the latest released frameworks that have supported open hardware integration for ML applications. Moreover, part of this work is devoted to the challenges that are concerned, such as power efficiency and reliability, when designing and building application with OSH in the AI/ML domain. This study presents a quantitative taxonomy of RISC-V SoC and reveals the opportunities in future research in machine learning with RISC-V open-source hardware architectures.
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spelling doaj.art-182d97d8a7554d4cb8f6914113d881162023-11-16T21:11:50ZengMDPI AGInformation2078-24892023-01-011426410.3390/info14020064A Survey on RISC-V-Based Machine Learning EcosystemStavros Kalapothas0Manolis Galetakis1Georgios Flamis2Fotis Plessas3Paris Kitsos4Electronic Circuits, Systems and Applications (ECSA) Laboratory, Electrical and Computer Engineering Department, University of Peloponnese, 26334 Patras, GreeceDepartment of Electrical and Computer Engineering, University of Thessaly, 38221 Volos, GreeceElectronic Circuits, Systems and Applications (ECSA) Laboratory, Electrical and Computer Engineering Department, University of Peloponnese, 26334 Patras, GreeceDepartment of Electrical and Computer Engineering, University of Thessaly, 38221 Volos, GreeceElectronic Circuits, Systems and Applications (ECSA) Laboratory, Electrical and Computer Engineering Department, University of Peloponnese, 26334 Patras, GreeceIn recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and applications that have already reached a substantial growth, such as in natural language processing (NLP) and computer vision (CV). The developments of open-source hardware (OSH) and the contribution towards the creation of hardware-based accelerators with implication mainly in machine learning (ML), has also been significant. In particular, the reduced instruction-set computer-five (RISC-V) open standard architecture has been widely adopted by a community of researchers and commercial users, worldwide, in numerous openly available implementations. The selection through a plethora of RISC-V processor cores and the mix of architectures and configurations combined with the proliferation of ML software frameworks for ML workloads, is not trivial. In order to facilitate this process, this paper presents a survey focused on the assessment of the ecosystem that entails RISC-V based hardware for creating a classification of system-on-chip (SoC) and CPU cores, along with an inclusive arrangement of the latest released frameworks that have supported open hardware integration for ML applications. Moreover, part of this work is devoted to the challenges that are concerned, such as power efficiency and reliability, when designing and building application with OSH in the AI/ML domain. This study presents a quantitative taxonomy of RISC-V SoC and reveals the opportunities in future research in machine learning with RISC-V open-source hardware architectures.https://www.mdpi.com/2078-2489/14/2/64RISC-Vopen-source hardwarehardware acceleratorsSoCCPUMCU
spellingShingle Stavros Kalapothas
Manolis Galetakis
Georgios Flamis
Fotis Plessas
Paris Kitsos
A Survey on RISC-V-Based Machine Learning Ecosystem
Information
RISC-V
open-source hardware
hardware accelerators
SoC
CPU
MCU
title A Survey on RISC-V-Based Machine Learning Ecosystem
title_full A Survey on RISC-V-Based Machine Learning Ecosystem
title_fullStr A Survey on RISC-V-Based Machine Learning Ecosystem
title_full_unstemmed A Survey on RISC-V-Based Machine Learning Ecosystem
title_short A Survey on RISC-V-Based Machine Learning Ecosystem
title_sort survey on risc v based machine learning ecosystem
topic RISC-V
open-source hardware
hardware accelerators
SoC
CPU
MCU
url https://www.mdpi.com/2078-2489/14/2/64
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