On Verification of PLC-Programs Written in the LD-Language
<p align="LEFT">We discuss some questions connected with the construction of a technology of analysing correctness of Programmable Logic Controller programs. We consider an example of modeling and automated verification of PLC-programs written in the Ladder Diagram language (includin...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Yaroslavl State University
2012-01-01
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| Series: | Моделирование и анализ информационных систем |
| Subjects: | |
| Online Access: | http://mais-journal.ru/jour/article/view/24 |
| Summary: | <p align="LEFT">We discuss some questions connected with the construction of a technology of analysing correctness of Programmable Logic Controller programs. We consider an example of modeling and automated verification of PLC-programs written in the Ladder Diagram language (including timed function blocks) of the IEC 61131-3 standard. We use the Cadence SMV for symbolic model checking. Program properties are written in the linear-time temporal logic LTL.</p> |
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| ISSN: | 1818-1015 2313-5417 |